把输出段与次态段合并即可
`timescale 1ns/1ns
module fsm2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
localparam S0 = 3'b000 ;
localparam S1 = 3'b001 ;
localparam S2 = 3'b010 ;
localparam S3 = 3'b011 ;
localparam S4 = 3'b100 ;
reg [2:0] state,nxt_state ;
always @(posedge clk or negedge rst) begin
if(!rst)
state <= S0 ;
else
state <= nxt_state ;
end
always @(*) begin
case(state)
S0 : begin nxt_state = data ? S1 : S0 ; flag = 1'b0 ; end
S1 : begin nxt_state = data ? S2 : S1 ; flag = 1'b0 ; end
S2 : begin nxt_state = data ? S3 : S2 ; flag = 1'b0 ; end
S3 : begin nxt_state = data ? S4 : S3 ; flag = 1'b0 ; end
S4 : begin nxt_state = data ? S1 : S0 ; flag = 1'b1 ; end
default : begin nxt_state = 3'b000 ; flag = 1'b0 ; end
endcase
end
//*************code***********//
endmodule
标签:wire,进阶,state,状态机,localparam,rst,input,二段式
From: https://www.cnblogs.com/icwangpu/p/17038615.html