跟上题基本类似，加了个sel选择
`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire sel ,
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
reg[2:0] d_cnt ;
wire d_cur ;
assign d_cur = d1 ? d1 : (d2 ? d2 : 0);
always @(posedge clk or negedge rst) begin
if(!rst)
d_cnt <= 'd0 ;
else if((d_cnt+d_cur>=3 & !sel)|(d_cnt+d_cur>=5 & sel))
d_cnt <= d_cur ;
else if(d1)
d_cnt <= d_cnt + 1 ;
else if(d2)
d_cnt <= d_cnt + 2 ;
else
d_cnt <= d_cnt ;
end
always @(posedge clk or negedge rst) begin
if(!rst) begin
out1 <= 'd0 ;
out2 <= 'd0 ;
out3 <= 'd0 ;
end
else if(!sel & (d_cnt+d_cur >= 3)) begin
out1 <= 1'b1 ;
out3 <= d_cnt+d_cur - 3 ;
out2 <= 1'b0 ;
end
else if(sel & (d_cnt+d_cur >= 5)) begin
out1 <= 1'b0 ;
out3 <= d_cnt+d_cur - 5 ;
out2 <= 1'b1 ;
end
else begin
out1 <= 1'b0 ;
out2 <= 'd0 ;
out3 <= 1'b0 ;
end
end
//*************code***********//
endmodule