直接采用0-5计数器,虽然题目说无占空比要求,但其实只有60%占空比才能通过
`timescale 1ns/1ns
module odd_div (
input wire rst ,
input wire clk_in,
output wire clk_out5
);
//*************code***********//
reg[2:0] cyc_cnt ;
reg clk_out ;
always @(posedge clk_in or negedge rst) begin
if(!rst)
cyc_cnt <= 'd0 ;
else if(cyc_cnt == 4)
cyc_cnt <= 'd0 ;
else
cyc_cnt <= cyc_cnt + 1 ;
end
always @(posedge clk_in or negedge rst) begin
if(!rst)
clk_out <= 1'b0 ;
else if(cyc_cnt==0 || cyc_cnt==2)
clk_out <= ~clk_out ;
else
clk_out <= clk_out ;
end
assign clk_out5 = clk_out ;
//*************code***********//
endmodule
标签:分频,wire,题目,进阶,clk,rst,占空比
From: https://www.cnblogs.com/icwangpu/p/17038571.html