功能
1. 单axi-stream 接口输入,axis输出。( 10bit rbg输出)
编辑
2. 使用xilinx hls 编写。
编辑
3. 配置寄存器有
#pragma HLS INTERFACE s_axilite port=height //宽
#pragma HLS INTERFACE s_axilite port=width //高
![点击并拖拽以移动](/i/l/?n=22&i=blog/3028029/202211/3028029-20221106125116183-313120139.gif)
效果
编辑
支持
支持xilinx 所有系列fpga
仿真
图像输出开始
编辑
一行图像
![](/i/ll/?i=8b2be2b61cd5416287d9d547491aa0f1.png)
编辑
图像结束
编辑
编辑
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (COR/TOW)
// bit 1 - ap_ready (COR/TOW)
// others - reserved
// 0x10 : Data signal of width
// bit 31~0 - width[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of height
// bit 31~0 - height[31:0] (Read/Write)
// 0x1c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XTPG_CONTROL_ADDR_AP_CTRL 0x00
#define XTPG_CONTROL_ADDR_GIE 0x04
#define XTPG_CONTROL_ADDR_IER 0x08
#define XTPG_CONTROL_ADDR_ISR 0x0c
#define XTPG_CONTROL_ADDR_WIDTH_DATA 0x10
#define XTPG_CONTROL_BITS_WIDTH_DATA 32
#define XTPG_CONTROL_ADDR_HEIGHT_DATA 0x18
#define XTPG_CONTROL_BITS_HEIGHT_DATA 32
![点击并拖拽以移动](/i/l/?n=22&i=blog/3028029/202211/3028029-20221106125116183-313120139.gif)