HDLbits第三天

出于对FPGA学习巩固的目的，同时也希望能锻炼自己对于Verilog的题目分析，让自己对HDL代码的理解加深，所以想坚持写一下关于HDLbits网站刷题的系列，计划是工作日每日5题目+分析，周末每日十题+分析（如果题目繁琐会减轻数量，以能够分析准确并理解为主）

Modules

Hierarchy

Module

module mod_a ( input in1, input in2, output out );
    // Module body
endmodule

使用上面的方式能够进行简单电路的模块化，通过简单的模块可以构成巨大的模块构造复杂的电路。

Module

Connecting Signals to Module Ports

There are two commonly-used methods to connect a wire to a port: by position or by name.

By position

The syntax to connect wires to ports by position should be familiar, as it uses a C-like syntax. When instantiating a module, ports are connected left to right according to the module's declaration. For example:
mod_a instance1 ( wa, wb, wc );
This instantiates a module of type and gives it an instance name of "instance1", then connects signal (outside the new module) to the first port () of the new module, to the second port (), and to the third port (). One drawback of this syntax is that if the module's port list changes, all instantiations of the module will also need to be found and changed to match the new module. mod_awain1wbin2wcout

By name

Connecting signals to a module's ports by name allows wires to remain correctly connected even if the port list changes. This syntax is more verbose, however.
mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) );
The above line instantiates a module of type named "instance2", then connects signal (outside the module) to the port named , to the port named , and to the port named . Notice how the ordering of ports is irrelevant here because the connection will be made to the correct name, regardless of its position in the sub-module's port list. Also notice the period immediately preceding the port name in this syntax. mod_awain1wbin2wcout

上面就是说了对于电路的模块化有两个方式，一种是通过位置接口进行模块化，一种是通过名称进行模块化。以我现在的水平感觉有点像教程视频里说的那种例化的过程。（目前我也是看一点学一点）

module top_module ( input a, input b, output out );

    mod_a inst(
        .in1(a),
        .in2(b),
        .out(out)
    );
    
endmodule

有点像写tb激励文件的接线。

Connecting ports by position

Module pos

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);

  mod_a inst(out1, out2, a, b, c, d);
  
endmodule

小模块的声明

Connecting ports by name

Module name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);

    mod_a inst(
        .out1(out1),
        .out2(out2),
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d)
    );
    
endmodule

例化过程

Three modules

module shift

module top_module ( input clk, input d, output q );
    
    wire q1;
    wire q2;
    
    my_dff u1_my_dff(
        .clk(clk),
        .d(d),
        .q(q1)
    );
    
    my_dff u2_my_dff(
        .clk(clk),
        .d(q1),
        .q(q2)
    );
    
    my_dff u3_my_dff(
        .clk(clk),
        .d(q2),
        .q(q)
    );
    
endmodule

简单实现了多个模块串联。

Modules and vector

Module shift8

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    
    wire [7:0]q1;
    wire [7:0]q2;
    wire [7:0]q3;

    my_dff8 u1_my_dff8(
        .clk(clk),
        .d(d),
        .q(q1)
    );
    
    my_dff8 u2_my_dff8(
        .clk(clk),
        .d(q1),
        .q(q2)
    );
    
    my_dff8 u3_my_dff8(
        .clk(clk),
        .d(q2),
        .q(q3)
    );
    
    always @(*)begin
        case(sel)
            2'd0 : begin
               q = d;
            end
            2'd1 : begin
               q = q1;
            end
            2'd2 : begin
               q = q2; 
            end
            2'd3 : begin
                q = q3;
            end
        endcase
    end
    
endmodule

注意wire [7:0]q1;的声明顺序，和使用时候的宽度顺序是不一样的。