HDLbits第二天

出于对FPGA学习巩固的目的，同时也希望能锻炼自己对于Verilog的题目分析，让自己对HDL代码的理解加深，所以想坚持写一下关于HDLbits网站刷题的系列，计划是工作日每日5题目+分析，周末每日十题+分析（如果题目繁琐会减轻数量，以能够分析准确并理解为主）

Vectors

Vectors

Vectors

wire [99:0] my_vector; // Declare a 100-element vector
assign out = my_vector[10]; // Part-select one bit out of the vector

Vector0

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration

    assign outv[2:0] = vec[2:0];
    assign o2 = vec[2];
    assign o1 = vec[1];
    assign o0 = vec[0];
    
endmodule

vector向量，定义的时候长度声明在前，使用的时候长度声明在后。

Vectors in more detail

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );

    assign out_hi = in[15:8];
    assign out_lo = in[7:0];
    
endmodule

向量是可以进行拆分赋值的，上面是一个小练习对高低位的分割。

Vector part select

Part-select can be used on both the left side and right side of an assignment

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};

endmodule

在这个方法之中我使用了一个{}符号作为组合符号，也可以一个assign语句一个assign语句的进行逐段赋值。

Bitwise operators

Vectorgates
Even though you cannot assign to a wire more than once, you can use a part select on the left-hand-side of an assign. You don't need to assign to the entire vector all in one statement.

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);

    assign out_or_bitwise = a[2:0] | b[2:0];
    assign out_or_logical = a[2:0] || b[2:0];
    assign out_not[2:0] = ~a[2:0];
    assign out_not[5:3] = ~b[2:0];
    
endmodule

对于多位的逻辑运算来说，写明位宽可能更好。

Gates4

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);

    assign out_and = & in;
    assign out_or = | in;
    assign out_xor = ^ in;
    
endmodule

Vector concatenation operator

Vector3

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};

endmodule

Vector reversal1

assign out[7:0] = in[0:7]; does not work because Verilog does not allow vector bit ordering to be flipped.
The concatenation operator may save a bit of coding, allowing for 1 assign statement instead of 8.

module top_module( 
    input [7:0] in,
    output [7:0] out
);

    assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
    
endmodule

Verilog本身是没有矢量反转的函数的，但是可以通过组合（串联运算符）的方式实现数据的反转。

Replication operator

module top_module (
    input [7:0] in,
    output [31:0] out );//

    assign out = {{24{in[7]}}, in};

endmodule

其实和Python一样也可以通过数字来表示复制。

More replication

Vector5

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    assign out = ~{{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ^ {5{a, b, c, d, e}};
    
endmodule

其实读懂题目的话就比较容易做了。