标签：HDLBits top object module 问题 vect Bcdadd100 input 399
HDLBits-Bcdadd100问题
知识点
reg [31:0] vect;
vect[ 0 +:8]; # 等同vect [7:0]
vect[15 -:8]; # 等同vect[15:8]
reg [0:31] vect;
vect[ 0 +:8]; # 等同vect[0: 7]
vect[15 -:8]; # 等同vect[8:15]
第一次回答
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
genvar i;
generate
for(i=0;i<100;i=i+1) begin:bcd_fadd_arr
bcd_fadd u_bcd_fadd(
a[i*4 +: 4],
b[i*4 +: 4],
i==0?cin:co[i-1],
i==99?cout:co[i],
sum[i]
);
end
endgenerate
endmodule
第一次结果
Error (10161): Verilog HDL error at top_module.v(13): object "co" is not declared. Verify the object name is correct. If the name is correct, declare the object. File: /home/h/work/hdlbits.8369168/top_module.v Line: 13
Error (10161): Verilog HDL error at top_module.v(14): object "co" is not declared. Verify the object name is correct. If the name is correct, declare the object. File: /home/h/work/hdlbits.8369168/top_module.v Line: 14
第二次回答
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire co[99:0];
genvar i;
generate
for(i=0;i<100;i=i+1) begin:bcd_fadd_arr
bcd_fadd u_bcd_fadd(
a[i*4 +: 4],
b[i*4 +: 4],
i==0?cin:co[i-1],
i==99?cout:co[i],
sum[i]
);
end
endgenerate
endmodule
第二次结果
# Hint: Output 'cout' has no mismatches.
# Hint: Output 'sum' has 407 mismatches. First mismatch occurred at time 5.
# Hint: Total mismatched samples is 407 out of 411 samples
第三次回答
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire co[99:0];
genvar i;
generate
for(i=0;i<100;i=i+1) begin:bcd_fadd_arr
bcd_fadd u_bcd_fadd(
a[i*4 +: 4],
b[i*4 +: 4],
i==0?cin:co[i-1],
i==99?cout:co[i],
sum[i*4 +:4]
);
end
endgenerate
endmodule
第三次结果
Status: Success!
标签：HDLBits,
top,
object,
module,
问题,
vect,
Bcdadd100,
input,
399
From： https://www.cnblogs.com/ptzcarl/p/16907609.html