知识点

无

第一次

回答

module top_module (input x, input y, output z);

    wire az1,az2,bz1,bz2;
    
    A IA1( .x(x), .y(y), .z(az1) );
    A IA2( .x(x), .y(y), .z(az2) );
    
    B IB1( .x(x), .y(y), .z(bz1) );
    B IB2( .x(x), .y(y), .z(bz2) );
    
    assign z = (az2 & bz2) ^ (az1 | bz1);
    
endmodule

module A (input x, input y, output z);
    assign z = (z ^ y) & x;
endmodule

module B (input x, input y, output z);
    assign z = ~( x ^ y );
endmodule

结果

# ** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 15 ps.
This usually means your code is broken and the simulator can't simulate it. It's often caused by having a combinational loop or a latch with race conditions that oscillates, causing the simulator to never settle to a fixed value at this particular point in the simulation. Combinational loops can occur if some combinational logic (including always@(*) blocks) consumes a signal that it modifies. It can sometimes be caused by thinking in C while writing Verilog. Look for Quartus Warning (10240 or 13012) or Info (10041) regarding inferred latches or unsafe latch behaviour.

第二次

回答

module top_module (input x, input y, output z);

    wire az1,az2,bz1,bz2;
    
    A IA1( .x(x), .y(y), .z(az1) );
    A IA2( .x(x), .y(y), .z(az2) );
    
    B IB1( .x(x), .y(y), .z(bz1) );
    B IB2( .x(x), .y(y), .z(bz2) );
    
    assign z = (az2 & bz2) ^ (az1 | bz1);
    
endmodule

module A (input x, input y, output z);
    assign z = (x ^ y) & x;
endmodule

module B (input x, input y, output z);
    assign z = ~( x ^ y );
endmodule

结果

Status: Success!