标签：cout HDLBits sum cin module 问题 fadd top Adder3
知识点
genvar i;
generate
for(i = 0; i < 3 ; i = i + 1 )
begin:fadd_arr
fadd fadd_inst(a[i],
b[i],
i==0?cin:cout[i-1],
cout[i],
sum[i]);
end
endgenerate
第一次
回答
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
genvar i;
generate
for(i = 0; i < 3 ; i = i + 1 )
begin:fadd_arr
fadd fadd_inst(a[i],
b[i],
i==0?cin:cout[i-1],
cout[i],
sum[i]);
end
endgenerate
endmodule
module fadd(
input a,b,cin;
output cout,sum);
assign {cout,sum} = a + b + cin;
endmodule
结果
Error (10170): Verilog HDL syntax error at top_module.v(23) near text: ";"; expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/h/work/hdlbits.8436235/top_module.v Line: 23
Error (10112): Ignored design unit "fadd" at top_module.v(22) due to previous errors File: /home/h/work/hdlbits.8436235/top_module.v Line: 22
第二次
回答
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
genvar i;
generate
for(i = 0; i < 3 ; i = i + 1 )
begin:fadd_arr
fadd fadd_inst(a[i],
b[i],
i==0?cin:cout[i-1],
cout[i],
sum[i]);
end
endgenerate
endmodule
module fadd(
input a,b,cin,
output cout,sum);
assign {cout,sum} = a + b + cin;
endmodule
结果
Status: Success!
标签：cout,
HDLBits,
sum,
cin,
module,
问题,
fadd,
top,
Adder3
From： https://www.cnblogs.com/ptzcarl/p/16920510.html