`
module top_module (
input clk,
input x,
output z
);
reg [2:0] s_cur;
reg [2:0] s_nex;
//传递状态
always@(posedge clk) begin
s_cur<=s_nex;
end
//确定下一状态
always@() begin
case(s_cur)
3'b000:
case(x)
0:s_nex=3'b100;
1:s_nex=3'b111;
endcase
3'b001:
case(x)
0:s_nex=3'b101;
1:s_nex=3'b110;
endcase
3'b010:
case(x)
0:s_nex=3'b100;
1:s_nex=3'b101;
endcase
3'b011:
case(x)
0:s_nex=3'b101;
1:s_nex=3'b100;
endcase
3'b100:
case(x)
0:s_nex=3'b000;
1:s_nex=3'b111;
endcase
3'b101:
case(x)
0:s_nex=3'b001;
1:s_nex=3'b110;
endcase
3'b110:
case(x)
0:s_nex=3'b000;
1:s_nex=3'b101;
endcase
3'b111:
case(x)
0:s_nex=3'b001;
1:s_nex=3'b100;
endcase
endcase
end
//根据状态算结果，如果使用时钟上升沿，z的结果将会晚一个时钟呈现
always@() begin
case(s_cur)
3'b000:z<=1;
default:z<=0;
endcase
end
endmodule
`
https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q4
标签：case,cur,HDLBits,b101,b100,endcase,笔记,状态机,nex From： https://www.cnblogs.com/snow-blog/p/18209515