此示例显示连接：TLM Port -> Port -> Export -> Export -> Imp_port
TLM TesetBench 组件：
—————————————————————
Name Type
—————————————————————
uvm_test_top basic_test
env environment
comp_a component_a
sub_comp_a_a sub_component_a_a
trans_out uvm_blocking_put_port
trans_out uvm_blocking_put_port
comp_b component_b
sub_comp_b_a sub_component_b_a
sub_comp_b_aa sub_component_b_a
trans_in uvm_blocking_put_imp
trans_in uvm_blocking_put_export
trans_in uvm_blocking_put_export
—————————————————————
在 sub_comp_a_a 中实现 TLM port
在 sub_comp_a_a 中实现 TLM 端口包括以下步骤，
1. 声明 uvm_blocking_put_port
2. 创建端口
3. 随机化事务类
4. 通过 put() 方法将事务发送到 comp_b
class sub_component_a_a extends uvm_component;
transaction trans;
uvm_blocking_put_port#(transaction) trans_out;
`uvm_component_utils(sub_component_a_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_out = new("trans_out", this);
endfunction : new
//---------------------------------------
// run_phase
//---------------------------------------
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
trans = transaction::type_id::create("trans", this);
void'(trans.randomize());
`uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Before calling port put method"),UVM_LOW)
trans_out.put(trans);
`uvm_info(get_type_name(),$sformatf(" After calling port put method"),UVM_LOW)
phase.drop_objection(this);
endtask : run_phase
endclass : sub_component_a_a
在 comp_a 中实现 TLM 端口
在 comp_a 中实现 TLM 端口包括以下步骤，
1. 声明 uvm_blocking_put_port
2. 创建端口
3. 将端口与 sub_comp_a_a 端口连接
`include "sub_component_a_a.sv"
class component_a extends uvm_component;
sub_component_a_a sub_comp_a_a;
uvm_blocking_put_port#(transaction) trans_out;
`uvm_component_utils(component_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_out = new("trans_out", this);
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
sub_comp_a_a = sub_component_a_a::type_id::create("sub_comp_a_a", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
sub_comp_a_a.trans_out.connect(trans_out);
endfunction : connect_phase
endclass : component_b在 sub_comp_b_aa 中实现 TLM Imp port
在 sub_comp_b_aa 中实现 TLM 端口包括以下步骤：
1. 声明 uvm_blocking_put_imp
2. 创建 imp 端口
3. 实现 put() 方法来接收事物
class sub_component_b_aa extends uvm_component;
transaction trans;
uvm_blocking_put_imp#(transaction,sub_component_b_aa) trans_in;
`uvm_component_utils(sub_component_b_aa)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_in = new("trans_in", this);
endfunction : new
//---------------------------------------
// Imp port put method
//---------------------------------------
virtual task put(transaction trans);
`uvm_info(get_type_name(),$sformatf(" Recived trans On IMP Port"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
endtask
endclass : sub_component_b_aa在 sub_comp_b_a 中实现 TLM export
在 sub_comp_b_a 中实现 TLM 端口包括以下步骤，
1. 声明 uvm_blocking_put_export
2. 创建 export 端口
3. 连接 export 与 sub_comp_b_aa 的 imp_port
`include "sub_component_b_aa.sv"
class sub_component_b_a extends uvm_component;
sub_component_b_aa sub_comp_b_aa;
uvm_blocking_put_export#(transaction) trans_in;
`uvm_component_utils(sub_component_b_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_in = new("trans_in", this);
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
sub_comp_b_aa = sub_component_b_aa::type_id::create("sub_comp_b_aa", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
trans_in.connect(sub_comp_b_aa.trans_in);
endfunction : connect_phase
endclass : sub_component_b_a在 comp_b 中实现 TLM export
在 comp_b 中实现 TLM 端口包括以下步骤，
1. 声明 uvm_blocking_put_export
2. 创建export
3. 将 export 连接到 sub_comp_b_a 的 export 端口
`include "sub_component_b_a.sv"
class component_b extends uvm_component;
sub_component_b_a sub_comp_b_a;
uvm_blocking_put_export#(transaction) trans_in;
`uvm_component_utils(component_b)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_in = new("trans_in", this);
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
sub_comp_b_a = sub_component_b_a::type_id::create("sub_comp_b_a", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
trans_in.connect(sub_comp_b_a.trans_in);
endfunction : connect_phase
endclass : component_b在env中将 comp_a port 与 comp_b export连接。
`include "transaction.sv"
`include "component_a.sv"
`include "component_b.sv"
class environment extends uvm_env;
//---------------------------------------
// Components Instantiation
//---------------------------------------
component_a comp_a;
component_b comp_b;
`uvm_component_utils(environment)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
comp_a = component_a::type_id::create("comp_a", this);
comp_b = component_b::type_id::create("comp_b", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
comp_a.trans_out.connect(comp_b.trans_in);
endfunction : connect_phase
endclass : environment
仿真结果：
UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
-----------------------------------------------------------
Name Type Size Value
-----------------------------------------------------------
uvm_test_top basic_test - @1823
env environment - @1890
comp_a component_a - @1922
sub_comp_a_a sub_component_a_a - @2036
trans_out uvm_blocking_put_port - @2138
trans_out uvm_blocking_put_port - @1973
comp_b component_b - @2006
sub_comp_b_a sub_component_b_a - @2173
sub_comp_b_aa sub_component_b_aa - @2203
trans_in uvm_blocking_put_imp - @2305
trans_in uvm_blocking_put_export - @2223
trans_in uvm_blocking_put_export - @2056
-----------------------------------------------------------
UVM_INFO sub_component_a_a.sv(29) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] tranaction randomized
UVM_INFO sub_component_a_a.sv(30) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2376
addr integral 4 'hb
wr_rd integral 1 'h1
wdata integral 8 'hd1
---------------------------------
UVM_INFO sub_component_a_a.sv(32) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] Before calling port put method
UVM_INFO sub_component_b_aa.sv(24) @ 0: uvm_test_top.env.comp_b.sub_comp_b_a.sub_comp_b_aa [sub_component_b_aa] Recived trans On IMP Port
UVM_INFO sub_component_b_aa.sv(25) @ 0: uvm_test_top.env.comp_b.sub_comp_b_a.sub_comp_b_aa [sub_component_b_aa] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2376
addr integral 4 'hb
wr_rd integral 1 'h1
wdata integral 8 'hd1
---------------------------------
UVM_INFO sub_component_a_a.sv(34) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] After calling port put method
UVM_INFO /xcelium20.09/tools//methodology/UVM/CDNS-1.2/sv/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /xcelium20.09/tools//methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER] 标签：sub,comp,component,Export,uvm,phase,trans,Port,TLM From： https://www.cnblogs.com/fuqiangblog/p/16659534.html