此示例显示连接：TLM Port -> Port -> Export -> Imp_port
TLM TesetBench 组件：
—————————————————————
Name Type
—————————————————————
uvm_test_top basic_test
env environment
comp_a component_a
sub_comp_a_a sub_component_a_a
trans_out uvm_blocking_put_port
trans_out uvm_blocking_put_port
comp_b component_b
sub_comp_b_a sub_component_b_a
trans_in uvm_blocking_put_imp
trans_in uvm_blocking_put_export
—————————————————————
在 sub_comp_a_a 中实现 TLM port
在 sub_comp_a_a 中实现 TLM port包括以下步骤，
1. 声明 uvm_blocking_put_port
2. 创建端口
3. 随机化事务类
4. 通过 put() 方法将事务发送到 comp_b
class sub_component_a_a extends uvm_component;
//Step-1. Declaring blocking port
uvm_blocking_put_port #(transaction) trans_out;
`uvm_component_utils(sub_component_a_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_out = new("trans_out", this); //Step-2. Creating the port
endfunction : new
//---------------------------------------
// run_phase
//---------------------------------------
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
trans = transaction::type_id::create("trans", this);
void'(trans.randomize()); //Step-3. randomizing the transction
`uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans,\n %s",trans.sprint()),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Before calling port put method"),UVM_LOW)
trans_out.put(trans); //Step-4. Sending trans through port put method
`uvm_info(get_type_name(),$sformatf(" After calling port put method"),UVM_LOW)
phase.drop_objection(this);
endtask : run_phase
endclass : sub_component_a_a在 comp_a 中实现 TLM port
1. 声明 uvm_blocking_put_port
2. 创建端口
3. 连接端口与 sub_comp_a_a 端口
class component_a extends uvm_component;
sub_component_a_a sub_comp_a_a;
//Step-1. Declaring blocking port
uvm_blocking_put_port#(transaction) trans_out;
`uvm_component_utils(component_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_out = new("trans_out", this); //Step-2. Creating the port
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
sub_comp_a_a = sub_component_a_a::type_id::create("sub_comp_a_a", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
sub_comp_a_a.trans_out.connect(trans_out); //Step-3.Connecting port with sub_comp_a_a port
endfunction : connect_phase
endclass : component_a在 sub_comp_b_a 中实现 TLM Imp port
在 sub_comp_b_a 中实现 TLM 端口包括以下步骤，
1. 声明 uvm_blocking_put_imp
2. 创建 imp 端口
3. 实现 put() 方法以接收事物
class sub_component_b_a extends uvm_component;
transaction trans;
//Step-1. Declaring blocking imp port
uvm_blocking_put_imp#(transaction,sub_component_b_a) trans_in;
`uvm_component_utils(sub_component_b_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_in = new("trans_in", this); //Step-2. Creating imp port
endfunction : new
//---------------------------------------
// Imp port put method
//---------------------------------------
//Step-3. Implementing imp port
virtual task put(transaction trans);
`uvm_info(get_type_name(),$sformatf(" Recived trans On IMP Port"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
endtask
endclass : sub_component_b_a在 comp_b 中实现 TLM export
在 comp_b 中实现 TLM 端口包括以下步骤，
1. 声明 uvm_blocking_put_export
2. 创建导出
3. 将导出连接到 imp 端口
class component_b extends uvm_component;
sub_component_b_a sub_comp_b_a;
//Step-1. Declaring blocking export
uvm_blocking_put_export#(transaction) trans_in;
`uvm_component_utils(component_b)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_in = new("trans_in", this); //Step-2. Creating export
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
sub_comp_b_a = sub_component_b_a::type_id::create("sub_comp_b_a", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
trans_in.connect(sub_comp_b_a.trans_in); //Step-3. Connecting export to the imp port
endfunction : connect_phase
endclass : component_b在env中将 comp_a port与 comp_b export连接。
function void connect_phase(uvm_phase phase);
comp_a.trans_out.connect(comp_b.trans_in); //Connecting port with export
endfunction : connect_phase
仿真结果：
UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
--------------------------------------------------------
Name Type Size Value
--------------------------------------------------------
uvm_test_top basic_test - @1820
env environment - @1887
comp_a component_a - @1919
sub_comp_a_a sub_component_a_a - @2033
trans_out uvm_blocking_put_port - @2135
trans_out uvm_blocking_put_port - @1970
comp_b component_b - @2003
sub_comp_b_a sub_component_b_a - @2170
trans_in uvm_blocking_put_imp - @2220
trans_in uvm_blocking_put_export - @2053
--------------------------------------------------------
UVM_INFO sub_component_a_a.sv(29) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] tranaction randomized
UVM_INFO sub_component_a_a.sv(30) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2283
addr integral 4 'hb
wr_rd integral 1 'h1
wdata integral 8 'hd1
---------------------------------
UVM_INFO sub_component_a_a.sv(32) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] Before calling port put method
UVM_INFO sub_component_b_a.sv(24) @ 0: uvm_test_top.env.comp_b.sub_comp_b_a [sub_component_b_a] Recived trans On IMP Port
UVM_INFO sub_component_b_a.sv(25) @ 0: uvm_test_top.env.comp_b.sub_comp_b_a [sub_component_b_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2283
addr integral 4 'hb
wr_rd integral 1 'h1
wdata integral 8 'hd1
---------------------------------
UVM_INFO sub_component_a_a.sv(34) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] After calling port put method
UVM_INFO /xcelium20.09/tools//methodology/UVM/CDNS-1.2/sv/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /xcelium20.09/tools//methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER] 标签：sub,示例,comp,component,uvm,phase,trans,Port,TLM From： https://www.cnblogs.com/fuqiangblog/p/16659251.html