跟上一题基本类似,多了个valid判定当前输入数据是否有效
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
reg [3:0] seq_shift ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
seq_shift <= 'd0 ;
else if(data_valid)
seq_shift <= {seq_shift[2:0],data} ;
else
seq_shift <= seq_shift ;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
match <= 1'b0 ;
else if(({seq_shift[2:0],data}==4'b0110)&&data_valid)
match <= 1'b1 ;
else
match <= 1'b0 ;
end
endmodule
标签:进阶,seq,1ns,clk,rst,牛客,序列,input
From: https://www.cnblogs.com/icwangpu/p/17026066.html