跟上一题类似
这里有人可能会用到casex,最好别用,有的工具可能不支持
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
reg [8:0] temp ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
temp <= 'd0 ;
else
temp <= {temp[7:0],a};
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
match <= 1'b0 ;
else if(temp[2:0]==3'b110 && temp[8:6] == 3'b011)
match <= 1'b1 ;
else
match <= 1'b0 ;
end
endmodule
标签:题目,进阶,temp,1ns,clk,牛客,rst,input
From: https://www.cnblogs.com/icwangpu/p/17023533.html