标签：VHDL attribute FAST Syntax vivado port SLEW
SLEW为配置了I/O标准的输出缓冲区指定了输出缓冲区转换速率
支持可编程输出转换速率。
架构支持
所有架构。
适用对象
•端口（get_Ports）
°连接输出或双向端口
•单元（get_cell）
°输出缓冲器（所有OBUF变体）
价值观
•慢速（默认）
•中等：适用于UltraScale体系结构，仅适用于高性能（HP）I/O。
•快速
Syntax
Verilog Syntax
To set this attribute when inferring I/O buffers, place the proper Verilog attribute syntax
before the top-level output port declaration.
(* DRIVE = "{SLOW|FAST}" *)
Verilog Syntax Example
// Sets the Slew rate to be FAST
(* SLEW = "FAST" *) output FAST_DATA,
VHDL Syntax
To set this attribute when inferring I/O buffers, place the proper VHDL attribute syntax
before the top-level output port declaration.
Declare the VHDL attribute as follows:
attribute SLEW : string;
Specify the VHDL attribute as follows:
attribute SLEW of port_name : signal is value;
Where
•
port_name
is a top-level output port.
VHDL Syntax Example
FAST_DATA : out std_logic;
attribute SLEW : string;
-- Sets the Slew rate to be FAST
attribute SLEW of STATUS : signal is “FAST”;
XDC Syntax
set_property SLEW value [get_ports port_name]
Where
•
port_name
is an output or bidirectional port.
XDC Syntax Example
# Sets the Slew rate to be FAST
set_property SLEW FAST [get_ports FAST_DATA]
标签：VHDL,
attribute,
FAST,
Syntax,
vivado,
port,
SLEW
From： https://blog.csdn.net/cckkppll/article/details/141475036