标签：wire RLOC clk sr inv vivado FD
相对位置（RLOC）约束定义了逻辑元素的相对位置
分配给一个集合，如H_set、HU_set或U_set。
当RTL源文件中存在RLOC时，H_SET、HU_SET或U_SET属性将得到
转换为合成网表中单元的只读RPM属性。RLOC
属性被保留，但在合成后成为只读属性。了解更多
有关使用这些属性和定义RPM的信息，请参阅Vivado设计套件
用户指南：使用约束（UG903）[参考文献19]。
提示：在构建分层RPM时，使用synth_design-platen_hierarchy none来确保
RLOC属性保留在其预期的层次结构级别上。
您可以定义集合中任何元素相对于其他元素的位置
设置，而不管整个组最终放置在目标设备上。For
例如，如果RLOC约束应用于以某种方式组织的一组八个触发器
列，映射器维护该列并将整个触发器组作为
单个单元。相比之下，LOC约束指定了设计的绝对位置
而不参考其他设计元素。
架构支持
所有架构。
适用对象
•RTL源文件中的实例或模块。
价值观
使用基于SLICE的XY坐标系指定相对位置约束。
RLOC=XmYn
哪里：
•m是一个表示X坐标值的整数。
•n是表示Y坐标值的整数。
提示：因为相对位置（RLOC）约束中的X和Y数字仅定义了顺序和
设计元素之间的关系，而不是它们在目标设备上的绝对位置，它们的
编号可以包括负整数。
Syntax
Verilog Syntax
The RLOC property is a Verilog attribute defining the relative placement of design elements
within a set specified by H_SET, HU_SET, or U_SET in the RTL source files. Place the Verilog
attribute immediately before the instantiation of a logic element.
(* RLOC = "XmYn", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
Verilog Example
The following Verilog module defines RLOC property for the shift register Flops in the ffs
hierarchical module.
module inv (input a, output z);
LUT1 #(.INIT(2'h1)) lut1 (.I0(a), .O(z));
endmodule // inv
module ffs
(
input clk,
input d,
output q
);
wire sr_0, sr_0n;
wire sr_1, sr_1n;
wire sr_2, sr_2n;
wire sr_3, sr_3n;
wire sr_4, sr_4n;
wire sr_5, sr_5n;
wire sr_6, sr_6n;
wire sr_7, sr_7n;
wire inr, inrn, outr;
inv i0 (sr_0, sr_0n);
inv i1 (sr_1, sr_1n);
inv i2 (sr_2, sr_2n);
inv i3 (sr_3, sr_3n);
inv i4 (sr_4, sr_4n);
inv i5 (sr_5, sr_5n);
inv i6 (sr_6, sr_6n);
inv i7 (sr_7, sr_7n);
inv i8 (inr, inrn);
(* RLOC = "X0Y0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
(* RLOC = "X0Y1" *) FD sr1 (.C(clk), .D(sr_2n), .Q(sr_1));
(* RLOC = "X0Y2" *) FD sr2 (.C(clk), .D(sr_3n), .Q(sr_2));
(* RLOC = "X0Y3" *) FD sr3 (.C(clk), .D(sr_4n), .Q(sr_3));
(* RLOC = "X0Y4" *) FD sr4 (.C(clk), .D(sr_5n), .Q(sr_4));
(* RLOC = "X0Y5" *) FD sr5 (.C(clk), .D(sr_6n), .Q(sr_5));
(* RLOC = "X0Y6" *) FD sr6 (.C(clk), .D(sr_7n), .Q(sr_6));
(* RLOC = "X0Y7" *) FD sr7 (.C(clk), .D(inrn), .Q(sr_7));
(* LOC = "SLICE_X0Y0" *) FD inq (.C(clk), .D(d), .Q(inr));
FD outq (.C(clk), .D(sr_0n), .Q(outr));
assign q = outr;
endmodule // ffs
TIP:
In the preceding example, the presence of the RLOC property implies the use of the H_SET property
on the FD instances in the ffs hierarchical module.
When using the modules defined in the preceding example, you will need to specify the
KEEP_HIERARCHY property to instances of the ffs module to preserve the hierarchy and
define the RPM in the synthesized design:
module top
(
input clk,
input d,
output q
);
wire c1, c2;
(* RLOC_ORIGIN = "X1Y1", KEEP_HIERARCHY = "YES" *) ffs u0 (clk, d, c1);
(* RLOC_ORIGIN = "X3Y3", KEEP_HIERARCHY = "YES" *) ffs u1 (clk, c1, c2);
(* RLOC_ORIGIN = "X5Y5", KEEP_HIERARCHY = "YES" *) ffs u2 (clk, c2, q);
endmodule // top
VHDL Syntax
Declare the VHDL constraint as follows:
attribute RLOC: string;
Specify the VHDL constraint as follows:
attribute RLOC of {component_name | entity_name | label_name} :
{component|entity|label} is “XmYn”;
Where:
• {
component_name
|
entity_name
|
label_name
} is a choice of one design element.
• {
component
|
entity
|
label
} is the instance ID of the design element.
•
XmYn
defines the RLOC value for the specified design element.
XDC Syntax
The RLOC property can not be defined using XDC constraints. The RLOC property defines
the relative locations of objects in a relatively placed macro (RPM), and results in read-only
RPM and RLOC properties in the netlist of synthesized designs.
标签：wire,
RLOC,
clk,
sr,
inv,
vivado,
FD
From： https://blog.csdn.net/cckkppll/article/details/141370007