SystemVerilog -- 3.8 SystemVerilog case

SystemVerilog case

SystemVerilog语句检查表达式是否与多个表达式和分支中的一个匹配。该行为与Verilog中的行为相同。case

unique, unique0 case

所有case语句都可以由or关键字限定，以执行违规检查，就像我们在if-else-if构造中看到的那样。unique unique0

unique并确保没有重叠的案例项，因此可以并行评估。如果存在重叠的案例项，则报告违规行为。unique

• 如果发现多个事例项与给定表达式匹配，则报告违规并执行第一个匹配表达式。
• 如果未发现与给定表达式匹配的案例项，则仅报告冲突。unique

unique: No items match for given expression

module tb;
  bit [1:0] abc;
  
  initial begin
    abc = 1;
    // None of the case items match the value in "abc"
    // A violation is reported here
    unique case (abc)
      0 : $display ("Found to be 0");
      2 : $display ("Found to be 2");
    endcase
  end
endmodule

模拟日志

ncsim> run
Found to be 0
ncsim: *W,MCONDE: Unique case violation: Every case item expression wa false.
        File: ./testbench.sv, line = 9, pos = 14
        Scope: tb
        Time: 0 FS + 1
ncsim: *W,RNQUIE: Simulation is complete.

unique: More then one case item match

module tb;
  bit [1:0] abc;

  initial begin
    abc = 0;

    // Multiple case items match the value in "abc"
    // A violation is reported here
    unique case (abc)
      0 : $display ("Found to be 0");
      0 : $display ("Again found to be 0");
      2 : $display ("Found to be 2");
    endcase
  end
endmodule

模拟日志

ncsim> run
Found to be 0
ncsim: *W,MCONDE: Unique case violation: Multiple matching case item expressions at {line=10:pos=6 and line=11:pos=6}.
        File: ./testbench.sv, line = 9, pos = 14
        Scope: tb
        Time: 0 FS + 1
ncsim: *W,RNQUIE: Simulation is complete.

priority case

module tb;
  bit [1:0] abc;

  initial begin
    abc = 0;
    
    // First match is executed
    priority case (abc)
      0 : $display ("Found to be 0");
      0 : $display ("Again found to be 0");
      2 : $display ("Found to be 2");
    endcase
  end
endmodule

模拟日志

ncsim> run
Found to be 0
ncsim: *W,RNQUIE: Simulation is complete.