SystemVerilog 'unique' and 'priority' if-else
条件语句用于决定是否执行语句。if else
SystemVerilog 引入了一下用于违规检查的构造。if else
- unique-if
- unique0-if
- priority-if
unique-if, unique0-if
unique-if
按任意顺序评估条件,并执行以下操作:
- 当所有条件都不匹配时,报告错误,除非有显示。
if else
- 当在条件中找到超过1个匹配项时报告ERORR。
if else
Unlike unique-if, unique0-if does not report a violation if none of the conditions match |
No else block for unique-if
module tb;
int x = 4;
initial begin
// This if else if construct is declared to be "unique"
// Error is not reported here because there is a "else"
// clause in the end which will be triggered when none of the conditions match
unique if (x == 3)
$display ("x is %0d", x);
else if (x == 5)
$display ("x is %0d", x);
else
$display ("x is neither 3 nor 5");
// When none of the conditions become true and there is no "else" clause, then an error is reported
unique if (x == 3)
$display ("x is %0d", x);
eles if (x == 5)
$display ("x is %0d", x);
end
endmodule
模拟日志
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Unique if violation: Every if clause was false.
File: ./testbench.sv, line = 18, pos = 13
Scope: tb
Time: 0 FS + 1
ncsim: *W,RNQUIE: Simulation is complete.
Multiple matches in unique-if
module tb;
int x = 4;
initial begin
// This if else if construct is declared to be "unique"
// When multiple if blocks match, then error is reported
unique if (x == 4)
$display ("1. x is %0d", x);
else if ()
$display ("2. x is %0d", x);
else
$display ("x is not 4");
end
endmodule
模拟日志
ncsim> run
1. x is 4
ncsim: *W,NOCOND: Unique if violation: Multiple true if clauses at {line=8:pos=15 and line=10:pos=13}.
File: ./testbench.sv, line = 8, pos = 15
Scope: tb
Time: 0 FS + 1
ncsim: *W,RNQUIE: Simulation is complete.
priority-if
priority-if
按顺序评估所有条件,并在以下情况下报告违规行为:
- 没有一个条件为真,或者如果最终构造没有子句。
else if
No else clause in priority-if
module tb;
int x = 4;
initial begin
// This if else if construct is declared to be "priority"
// Error is not reported here because there is a "else"
// clause in the end which will be triggered when none of the conditions match
priority if (x == 3)
$display ("x is %0d", x);
else if (x == 5)
$display ("x is %0d", x);
else
$display ("x is neither 3 nor 5");
// When none of the conditions become true and there is no "else" clause, then an error is reported
priority if (x == 3)
$display ("x is %0d", x);
else if (x == 5)
$display ("x is %0d", x);
end
endmodule
模拟日志
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Unique if violation: Every if clause was false.
File: ./testbench.sv, line = 18, pos = 15
Scope: tb
Time: 0 FS + 1
ncsim: *W,RNQUIE: Simulation is complete.
Exit after first match in priority-if
module tb;
int x = 4;
initial begin
// Exits if-else block once the first match is found
priority if (x == 4)
$display ("x is %0d", x);
else if (x != 5)
$display ("x is %0d", x);
end
endmodule
模拟日志
ncsim> run
x is 4
ncsim: *W,RNQUIE: Simulation is complete.
标签:ncsim,--,else,priority,0d,unique,display,SystemVerilog
From: https://www.cnblogs.com/sys-123456/p/18173812