1.CYT2BL address map
• 4160 KB (4032 KB + 128 KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in
the flash control register
- Single-bank mode - 4160 KB
- Dual-bank mode - 2080 KB per bank
• 128 KB (96 KB + 32 KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the
flash control register - Single-bank mode - 128 KB
- Dual-bank mode - 64 KB per bank
• 32 KB of secure ROM
• 512 KB of SRAM (First 2 KB is reserved for internal usage)
2.CYT2BL启动时序
The following steps describe the start-up sequence:
- System Reset (@0x0000 0000)
- CM0+ executes ROM boot (@0x0000 0004)
- Applies trims
- Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisoryflash
- Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
- CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
- Debug pins are configured as per the SWD/JTAG spec [17]
- Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash(@0x1000 0000)
- CM0+ branches to its Reset handler
- CM0+ starts execution
- Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
- Sets CM4_VECTOR_TABLE_BASE (@0x0000 0200) to the location of CM4 vector table mentioned in flash(specified in CM4 linker definition file)
- Releases CM4 from reset
- Continues execution of CM0+ user application
- CM4 executes directly from either code-flash or SRAM
- CM4 branches to its Reset handler
- Continues execution of CM4 user application
3.SFlash
用于存储修剪参数、系统配置参数、保护和安全设置、引导脚本等,可以称之为sflash。
4.Power modes
CYT2BL has six different power modes:
- Active – All peripherals are available
- Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are available, but with limited capability
- Sleep – All peripherals except the CPUs are available
- Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are available, but with limited capability
- DeepSleep – Only peripherals which work with CLK_LF are available
- Hibernate – the device and I/O states are frozen, the device resets on wakeup