FPGA 让2个LED灯按照设置的模式各自在一个变化循环内独立亮灭变化

代码如下：

//让多个LED灯按照设置的模式各自在一个变化循环内独立亮灭变化。
module counter_led_5(
    Clk,
    Reset_n,
    CtrlA,
    CtrlB,
    Time,
    Led
);
    input Clk;
    input Reset_n;
    input [7:0]CtrlA;
    input [7:0]CtrlB;
    input [31:0]Time;
    output reg [1:0]Led;
 
    reg [31:0]counter;
    
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        counter <= 0;
    else if(counter == Time - 1)
        counter <= 0;
    else
        counter <= counter + 1'b1;
    
    reg [2:0]counter2;
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n) 
        counter2 <= 0; 
    else if(counter == Time - 1)
        counter2 <= counter2 + 1'b1;
 
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        Led <= 2'd0;
    else case(counter2)
        0:begin Led[0] <= CtrlA[0]; Led[1] <= CtrlB[0]; end
        1:begin Led[0] <= CtrlA[1]; Led[1] <= CtrlB[1]; end
        2:begin Led[0] <= CtrlA[2]; Led[1] <= CtrlB[2]; end
        3:begin Led[0] <= CtrlA[3]; Led[1] <= CtrlB[3]; end
        4:begin Led[0] <= CtrlA[4]; Led[1] <= CtrlB[4]; end
        5:begin Led[0] <= CtrlA[5]; Led[1] <= CtrlB[5]; end
        6:begin Led[0] <= CtrlA[6]; Led[1] <= CtrlB[6]; end
        7:begin Led[0] <= CtrlA[7]; Led[1] <= CtrlB[7]; end
        default:begin Led[0] <= Led; Led[1] <= Led[1]; end
    endcase
            
endmodule

仿真代码如下：

`timescale 1ns/1ns
 
module counter_led_5_tb;
 
    reg Clk;
    reg Reset_n;
    reg [7:0]CtrlA,CtrlB;
    reg [31:0]Time;
    wire [1:0]Led;
 
    counter_led_5 counter_led_5(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .CtrlA(CtrlA),
        .CtrlB(CtrlB),
        .Time(Time),
        .Led(Led)
    );
    
    initial Clk = 1;
    always #10 Clk = !Clk;
    
    initial begin
        Reset_n = 0;
        CtrlA = 0;
        CtrlB = 0;
        Time = 0;
        #201;
        Reset_n = 1;
        #2000;
        Time = 2500;
        CtrlA = 8'b1000_0110;
        CtrlB = 8'b1101_0010;
        #20000000;  
        Time = 25000;
        CtrlA = 8'b1010_0110;
        CtrlB = 8'b1100_1010;
        #20000000;    
        $stop;
    end
    
endmodule