`timescale 1ns/1ps
module  data_cnt (
    input clk,     //50MHZ  20ns
    input rstn,
    input trig,    //触发信号 一个时钟周期

    output wire state   //得到1us的高脉冲信号
);


//define
reg [5:0]  data_cnt;    //1us 50 
reg        data_cnt_clr;

//----------------1us计数器----------------//
always @(posedge clk or negedge rstn) begin
    if (!rstn) 
        data_cnt <= 6'd0;
    else if(!data_cnt_clr)   // 等于0  data_cnt = 0
        data_cnt <= 6'd0;
    else 
        data_cnt <= data_cnt + 1'b1;
end


//---------------得到一个1us的高脉冲信号state----------------//
always @(posedge clk or negedge rstn) begin
  if (!rstn) 
    begin
        data_cnt_clr <= 1'b0;  
    end
  else if(trig == 1 && data_cnt == 6'd0)
        begin
            data_cnt_clr <= 1'b1;  
        end
  else if(data_cnt == 50 - 1) 
    begin
        data_cnt_clr <= 1'b0;
    end
  else
    begin
        data_cnt_clr <= data_cnt_clr; 
    end     
end

 assign state = data_cnt_clr;

endmodule

`timescale 1ns / 1ps
module data_cnt_tb;

  // Parameters

  // Ports
  reg clk  ;
  reg rstn ;
  reg trig ;

  wire state;

  data_cnt 
  data_cnt_dut (
    .clk    (clk    ),
    .rstn   (rstn   ),
    .trig   (trig   ),
    .state  (state  )
  );

  initial begin
    begin
          clk = 0;
          rstn = 0;
          trig = 0;
          
    #20   rstn = 1;
    #500  
          trig = 1;
    #20   trig = 0;

    #1200
          trig = 1;
    #20   trig = 0;

    end
  end

  always
    #10  clk = ! clk ;

endmodule