FPGA 舵机控制

module dj(clock,good0,good1,good2,good3,good4,en_duoji,money,pwm_out0,pwm_out1,pwm_out2,pwm_out3,pwm_out4); 
input clock;
input money;
input en_duoji;
input good0,good1,good2,good3,good4;
output reg pwm_out0;
output reg pwm_out1;
output reg pwm_out2;
output reg pwm_out3;
output reg pwm_out4;

reg [32:0]counter;
reg [32:0]counter1;

initial 
begin
pwm_out0='b0;
pwm_out1='b0;
pwm_out2='b0;
pwm_out3='b0;
pwm_out4='b0;
counter='d0;
counter1='d0;
end

always@(posedge clock)
begin
    if(en_duoji &&~money)
        counter=counter+1;
        if(counter==32'd5000)
            begin
            counter=0;
            counter1=counter1+1;
            end
        if(counter1==8'd1)begin
            if(good0)begin
            pwm_out0<='b1;end
            if(good1)begin
            pwm_out1<='b1;end
            if(good2)begin
            pwm_out2<='b1;end
            if(good3)begin
            pwm_out3<='b1;end
            if(good4)begin
            pwm_out4<='b1;end        
        end    
        else if(counter1==8'd20)begin
            pwm_out0<='b0;
            pwm_out1<='b0;
            pwm_out2<='b0;
            pwm_out3<='b0;
            pwm_out4<='b0;end
        else if(counter1==16'd200)
            counter1=0;
end
endmodule

clock为输入时钟信号

good0-4为选择舵机的信号

pwm_out0-1为输出的pwm信号

en_duoji和money用于控制  en_duoji为高 && money为低 舵机才会转动