FPGA HC-SR04

module distance(clock, clr_n,trig,echo,out_dis);
input clock,clr_n;//时钟信号 复位信号
input echo;//测距模块
output reg trig;//测距模块
output reg out_dis;//输出 此处用于控制LED

reg[21:0]counter_distance;//计时 每60ms
integer counter_echo;//计时echo高电平

initial 
begin
trig='b0;
out_dis='b0;
counter_distance=22'd0;
counter_echo=0;
end

always@(posedge clock or negedge clr_n)//用于计时60ms
begin
    if(!clr_n)
    ;
    else
    begin
        if(counter_distance<22'd300_0000)
            counter_distance<=counter_distance+1'b1;
        else
            counter_distance<=22'd0;
        end
end

always@(counter_distance)//用于向测距模块发送触发
begin
    if(counter_distance<22'd500)
        trig<='b1;
    else
        trig<='b0;
end

always@(posedge clock)
begin
    if(echo=='b1)
        counter_echo<=counter_echo+1;
    else if(counter_distance==22'd300_0000)
    begin
        counter_echo<=0;
    end
    else if(counter_echo>0)
            if(counter_echo*34<1000000)//用10cm计算
                out_dis<='b1;
    else
        out_dis<='b0;
end
        
endmodule