module hope(clock,clr_n,Sound_in,Sound_o);
input clock;
input clr_n;
input [2:0]Sound_in;
output reg[4:0] Sound_o;
reg en_1;
reg[27:0]counter;
reg[2:0]temp;
initial
begin
Sound_o=5'b1_1111;
counter=28'd0;
en_1='b0;
temp=3'b000;
end
always@(posedge clock or negedge clr_n)begin
if(!clr_n)
counter<=28'd0;
else
begin
if(en_1=='b0)begin
counter<=28'd0;
end
else
begin
if(counter<28'd2_5000_0000)begin
counter<=counter+1'b1;
end
else
counter<=28'd0;
temp<=Sound_in;
end
end
end
always@(Sound_in or counter)begin
if(Sound_in!=temp)
en_1<='b1;
else if(counter<28'd2_5000_0000 && counter>28'd0)
en_1<='b1;
else
en_1<='b0;
end
always@(posedge clock or negedge clr_n)begin
if(!clr_n)begin
Sound_o<=5'b1_1111;
end
else if(counter>28'b0 && counter<28'd2_5000_0000)begin
case(Sound_in)
3'b001:Sound_o<=5'b0_1111;
3'b011:Sound_o<=5'b1_0111;
3'b111:Sound_o<=5'b0_0111;
3'b010:Sound_o<=5'b1_1011;
3'b100:Sound_o<=5'b0_0001;
default:Sound_o<=5'b1_1111;
endcase
end
else
begin Sound_o<=5'b1_1111; end
end
endmodule
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标签：Sound,en,fpga,clock,m3,input,ys,reg,clr From： https://www.cnblogs.com/lyhthebest/p/16883483.html