1 Combinational Logic
1.1 Basic Gates
1.1.1 Exams/m2014 q4h
module top_module (
input in,
output out);
assign out = in;
endmodule
1.1.2 Exams/m2014 q4i
module top_module (
output out);
assign out = 1'b0;
endmodule
1.1.3 Exams/m2014 q4e
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1|in2);
endmodule
1.1.4 Exams/m2014 q4f
module top_module (
input in1,
input in2,
output out);
assign out = in1&(~in2);
endmodule
1.1.5 Exams/m2014 q4g
module top_module (
input in1,
input in2,
input in3,
output out);
wire out1;
assign out1 = in1^in2;
assign out = ~(out1^in3);
endmodule
1.1.6 Gates
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a&b;
assign out_or = a|b;
assign out_xor = (a^b);
assign out_nand = ~(a&b);
assign out_nor = ~(a|b);
assign out_xnor = ~(a^b);
assign out_anotb = a&~b;
endmodule
1.1.7 7420
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a&p1b&p1c&p1d);
assign p2y = ~(p2a&p2b&p2c&p2d);
endmodule
1.1.8 Truthtable1
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (x3&x1)|(~x3&x2);
endmodule
1.1.9 Mt2015 eq2
module top_module ( input [1:0] A, input [1:0] B, output z );
always @(*)begin
if(A==B)
z = 1;
else
z = 0;
end
endmodule
1.1.10 Mt2015 q4a
module top_module (input x, input y, output z);
assign z = (x ^ y) & x;
endmodule
1.1.11 Mt2015 q4b
module top_module ( input x, input y, output z );
assign z = ~(x^y);
endmodule
1.1.12 Mt2015 q4
module top_module (input x, input y, output z);
wire [3:0] z_pr;
IA U1(x,y,z_pr[0]);
IB L1(x,y,z_pr[1]);
IA U2(x,y,z_pr[2]);
IB L2(x,y,z_pr[3]);
assign z = (z_pr[0]|z_pr[1])^(z_pr[2]&z_pr[3]);
endmodule
module IA(input a,input b, output c);
assign c = (a ^ b) & a;
endmodule
module IB(input a,input b, output c);
assign c = ~(a^b);
endmodule
1.1.13 Ringer
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ring & (~vibrate_mode);
assign motor = ring & vibrate_mode;
endmodule
1.1.14 Thermostat
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode&too_cold;
assign aircon = too_hot&~mode;
assign fan = (heater | aircon) | fan_on;
endmodule
1.1.15 Popcount3
module top_module(
input [2:0] in,
output [1:0] out );
integer i;
always @(*) begin
out = 0;
for(i = 0; i < 3; i ++) begin
if(in[i])
out++;
end
end
endmodule
1.1.15 Popcount3
module top_module(
input [2:0] in,
output [1:0] out );
integer i;
always @(*) begin
out = 0;
for(i = 0; i < 3; i ++) begin
if(in[i])
out++;
end
end
endmodule
1.1.16 Gatesv
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
integer i;
always @(*)begin
for(i = 0;i<3;i++)
begin
out_both[i] = in[i]&in[i+1];
out_any[i+1] = in[i]|in[i+1];
out_different[i] = in[i]^in[i+1];
end
out_different[3] = in[3]^in[0];
end
endmodule
1.1.17 Gatesv100
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
integer i;
always @(*)begin
for(i = 0;i<99;i++)
begin
out_both[i] = in[i]&in[i+1];
out_any[i+1] = in[i]|in[i+1];
out_different[i] = in[i]^in[i+1];
end
out_different[99] = in[99]^in[0];
end
endmodule
## 1.2 Multiplexers
### 1.2.1 Mux2to1
module top_module(
input a, b, sel,
output out );
always @(*)begin
case(sel)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
### 1.2.2 Mux2to1v
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
always @(*)begin
case(sel)
1'b0:out=a;
1'b1:out=b;
endcase
end
endmodule
### 1.2.3 Mux9to1v
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always @(*) begin
case(sel)
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
4 : out = e;
5 : out = f;
6 : out = g;
7 : out = h;
8 : out = i;
default : out = 16'hffff;
endcase
end
endmodule
### 1.2.4 Mux256to1
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
endmodule
### 1.2.5 Mux256to1v
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out = {in[4sel+3],in[4sel+2],in[4sel+1],in[4sel]};
endmodule
## 1.3 Arithmetic Circuits
###