标签：计算机 16 21845 21846 笔记 0000000000000000 原理 sel out

计算机组成原理

author: Ahtelek date: 11/1/2022

概述

计算机系统

计算机组成要素: 冯诺依曼体系结构

运算器, CA: central arithmetical
控制器, CC: central control
储存器, M: memory
输入设备, I: input
输出设备, O: output

地址: 每个存储单元对应的序号
内容: 存储单元中存放的信息

哈佛结构

将指令和数据放在两个独立的存储器, 允许在一个机器周期内同时获得指令和操作数, 提高了执行速度.

执行指令: 计算机运算的核心内容

计算机执行一条指令的主要步骤

第一步: 取指(Fetch)
第二部: 译码(Decode)
第三步: 执行(Execute)
第四步: 回写(Write-back)

晶体管

现代集成电路中通常使用MOS晶体管
Metal-Oxide-Semiconductor: 金属-氧化物-半导体
CMOS集成电路(Complementary MOS)
由PMOS和NMOS共同构成的互补型MOS集成电路

N型MOS管

高电平有效

P型MOS管

低电平有效

NOT gate(非门)

真值表

输入	输出
0	1
1	0

逻辑表达式: out=in'
非门原理图

AND gate(与门)

真值表

输入A	输入B	输出Y
0	0	0
0	1	0
1	0	0
1	1	1

逻辑表达式: Y=AB

Nand gate(与非门)

真值表

输入A	输入B	输出Y
0	0	1
0	1	1
1	0	1
1	1	0

逻辑表达式: Y=(AB)'

Nor gate(或非门)

真值表

输入A	输入B	输出Y
0	0	1
0	1	0
1	0	0
1	1	0

逻辑表达式: Y=(A+B)'

100

布尔代数与基本门电路

逻辑运算: 与/或/非/异或

与运算:有0则0, 全1则1

A	B	A&B
0	0	0
0	1	0
1	0	0
1	1	1

或运算: 有1则1. 全0则0

A	B	A\|B
0	0	0
0	1	1
1	0	1
1	1	1

非运算: 0则1, 1则0

A	A'
0	1
1	0

异或运算: 异则1, 同则0

A	B	A
0	0	0
0	1	1
1	0	1
1	1	0

布尔代数

序号	名称	公式1	公式2
1	交换律	a+b=b+a	ab=ba
2	结合律	a+(b+c)=(a+b)+c	a(bc)=(ab)c
3	分配律	a+bc=(a+b)(a+c)	a(b+c)=ab+ac
4	0-1律1	0+a=a	1a=a
5	0-1律2	1+a=1	0a=0
6	互补律	a+a'=1	aa'=0
7	吸收律1	a+ab=a	a(a+b)=a
8	吸收律2	a+a'b=a+b	a(a'+b)=ab
9	重叠律	a+a=a	aa=a
10	反演律	(a+b)'=a'b'	(ab)'=a'+b'
11	结合律(对合律)	(a')'=a
12	包含律	ab+a'c+bc=ab+a'c	(a+b)(a'+c)(b+c)=(a+b)(a'+c)

硬件描述语言

HDL语言的书写规则

CHIP 芯片名称(注意与文件名要同名){
    IN 输入引脚;
    OUT 输出引脚;

    PARTS:
    里面的组成部件电路
}

Not(非门)

真值表

a	b
0	1
1	0

逻辑表达式

Not(in)=Nand(in, in)
构建思路

使用Nand门, 构建Not门
电路图

代码实现

CHIP Not {
    IN in;
    OUT out;

    PARTS:
    Nand(a=in, b=in, out=out);
}

运行结果

Not16(16位非门)

真值表

in	out
0000000000000000	1111111111111111
1111111111111111	0000000000000000
1010101010101010	0101010101010101
0011110011000011	1100001100111100
0001001000110100	1110110111001011

逻辑表达式

Not16(in[16])=Not(in[0...15])
构建思路

使用Not门, 构建Not16门
电路图

代码实现

CHIP Not16 {
    IN in[16];
    OUT out[16];

    PARTS:
    Not(in=in[0], out=out[0]);
    Not(in=in[1], out=out[1]);
    Not(in=in[2], out=out[2]);
    Not(in=in[3], out=out[3]);
    Not(in=in[4], out=out[4]);
    Not(in=in[5], out=out[5]);
    Not(in=in[6], out=out[6]);
    Not(in=in[7], out=out[7]);
    Not(in=in[8], out=out[8]);
    Not(in=in[9], out=out[9]);
    Not(in=in[10], out=out[10]);
    Not(in=in[11], out=out[11]);
    Not(in=in[12], out=out[12]);
    Not(in=in[13], out=out[13]);
    Not(in=in[14], out=out[14]);
    Not(in=in[15], out=out[15]);
}

运行结果

And(与门)

真值表

a	b	out
0	0	0
0	1	0
1	0	0
1	1	1

逻辑表达式

And(a, b)=(Not(Nand(a, b)))
构建思路

使用Not门, Nand门, 构建And门
电路图

代码实现

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
    Nand(a=a, b=b, out=x);
    Not(in=x, out=out);

运行结果

And16(16位与门)

真值表

a	b	out
0000000000000000	0000000000000000	0000000000000000
0000000000000000	1111111111111111	0000000000000000
1111111111111111	1111111111111111	1111111111111111
1010101010101010	0101010101010101	0000000000000000
0011110011000011	0000111111110000	0000110011000000
0001001000110100	1001100001110110	0001000000110100

逻辑表达式

And16(a, b)=And(a[0...15], b[0...15])
构建思路

使用And门, 构建And16门
电路图

代码实现

CHIP And16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    And(a=a[0], b=b[0], out=out[0]);
    And(a=a[1], b=b[1], out=out[1]);
    And(a=a[2], b=b[2], out=out[2]);
    And(a=a[3], b=b[3], out=out[3]);
    And(a=a[4], b=b[4], out=out[4]);
    And(a=a[5], b=b[5], out=out[5]);
    And(a=a[6], b=b[6], out=out[6]);
    And(a=a[7], b=b[7], out=out[7]);
    And(a=a[8], b=b[8], out=out[8]);
    And(a=a[9], b=b[9], out=out[9]);
    And(a=a[10], b=b[10], out=out[10]);
    And(a=a[11], b=b[11], out=out[11]);
    And(a=a[12], b=b[12], out=out[12]);
    And(a=a[13], b=b[13], out=out[13]);
    And(a=a[14], b=b[14], out=out[14]);
    And(a=a[15], b=b[15], out=out[15]);
}

运行结果

Or (或门)

真值表

a	b	out
0	0	0
0	1	1
1	0	1
1	1	1

逻辑表达式

Or(a, b)=Not(And(Not(a), Not(b)))
构建思路

使用Not门, And门, 构建Or门
电路图

代码实现

CHIP Or {
    IN a, b;
    OUT out;

    PARTS:
    Not(in=a, out=outa);
    Not(in=b, out=outb);
    And(a=outa, b=outb, out=x);
    Not(in=x, out=out);
}

运行结果

Or16 (16位或门)

真值表

a	b	out
0000000000000000	0000000000000000	0000000000000000
0000000000000000	1111111111111111	1111111111111111
1111111111111111	1111111111111111	1111111111111111
1010101010101010	0101010101010101	1111111111111111
0011110011000011	0000111111110000	0011111111110011
0001001000110100	1001100001110110	1001101001110110

逻辑表达式

Or16(a,b)=Or(a[0...15], b[0...15])
构建思路

使用Or门, 构建Or16门
电路图

代码实现

CHIP Or16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    Or(a=a[0], b=b[0], out=out[0]);
    Or(a=a[1], b=b[1], out=out[1]);
    Or(a=a[2], b=b[2], out=out[2]);
    Or(a=a[3], b=b[3], out=out[3]);
    Or(a=a[4], b=b[4], out=out[4]);
    Or(a=a[5], b=b[5], out=out[5]);
    Or(a=a[6], b=b[6], out=out[6]);
    Or(a=a[7], b=b[7], out=out[7]);
    Or(a=a[8], b=b[8], out=out[8]);
    Or(a=a[9], b=b[9], out=out[9]);
    Or(a=a[10], b=b[10], out=out[10]);
    Or(a=a[11], b=b[11], out=out[11]);
    Or(a=a[12], b=b[12], out=out[12]);
    Or(a=a[13], b=b[13], out=out[13]);
    Or(a=a[14], b=b[14], out=out[14]);
    Or(a=a[15], b=b[15], out=out[15]);
}

运行结果

Or8Way (8位一输出或门)

真值表

in	out
00000000	0
11111111	1
00010000	1
00000001	1
00100110	1

逻辑表达式

Or8Way(a)=Or(in[0]...in[8])
构建思路

使用Or门, 构建Or8Way门
电路图

代码实现

CHIP Or8Way {
    IN in[8];
    OUT out;

    PARTS:
    Or(a=in[0],b= in[1],out=tp1);
    Or(a=in[2],b=in[3],out=tp2);
    Or(a=in[4],b=in[5],out=tp3);
    Or(a=in[6],b=in[7],out=tp4);
    Or(a=tp1,b=tp2,out=tp5);
    Or(a=tp3,b=tp4,out=tp6);
    Or(a=tp5,b=tp6,out=out);
}

运行结果

Xor (异或)

真值表

a	b	out
0	0	0
0	1	1
1	0	1
1	1	0

逻辑表达式

Xor(a, b)=Or(And(Not(a), b), And(a, Not(b)))
构建思路

使用Not门, And门, Or门, 构建Xor门
电路图

代码实现

CHIP Xor {
    IN a, b;
    OUT out;

    PARTS:
    Not(in=a, out=nota);
    Not(in=b, out=notb);
    And(a=nota, b=b, out=x1);
    And(a=a, b=notb, out=x2);
    Or(a=x1, b=x2, out=out);
}

运行结果

Mux(二选一数据选择器)

真值表

a	b	sel	out
0	0	0	0
1	0	0	1
0	1	0	0
1	1	0	1
0	0	1	0
1	0	1	0
0	1	1	1
1	1	1	1

逻辑表达式

Or(And(Not(sel), a), And(sel, b))
构建思路

使用Not/And/Or门电路, 构建Mux门
电路图

代码实现

CHIP Mux {    
 IN a, b, sel;
 OUT out;

 PARTS:
 Not(in=sel, out=Nsel);
 And(a=Nsel, b=a, out=nsel);
 And(a=sel, b=b, out=Asel);
 Or(a=Ansel, b=Asel, out=out);
}

运行结果

Mux16(16位数据选择器)

真值表

a	b	sel	out
0000000000000000	0000000000000000	0	0000000000000000
0000000000000000	0000000000000000	1	0000000000000000
0000000000000000	0001001000110100	0	0000000000000000
0000000000000000	0001001000110100	1	0001001000110100
1001100001110110	0000000000000000	0	1001100001110110
1001100001110110	0000000000000000	1	0000000000000000
1010101010101010	0101010101010101	0	1010101010101010
1010101010101010	0101010101010101	1	0101010101010101

逻辑表达式

Mux(a[16], n[16], sel)
构建思路

使用Mux, 构建Mux16门
电路图

代码实现

CHIP Mux16 {
    IN a[16], b[16], sel;
    OUT out[16];

    PARTS:
    // Put your code here:
    Mux(a=a[0], b=b[0], sel=sel, out=out[0]);
    Mux(a=a[1], b=b[1], sel=sel, out=out[1]);
    Mux(a=a[2], b=b[2], sel=sel, out=out[2]);
    Mux(a=a[3], b=b[3], sel=sel, out=out[3]);
    Mux(a=a[4], b=b[4], sel=sel, out=out[4]);
    Mux(a=a[5], b=b[5], sel=sel, out=out[5]);
    Mux(a=a[6], b=b[6], sel=sel, out=out[6]);
    Mux(a=a[7], b=b[7], sel=sel, out=out[7]);
    Mux(a=a[8], b=b[8], sel=sel, out=out[8]);
    Mux(a=a[9], b=b[9], sel=sel, out=out[9]);
    Mux(a=a[10], b=b[10], sel=sel, out=out[10]);
    Mux(a=a[11], b=b[11], sel=sel, out=out[11]);
    Mux(a=a[12], b=b[12], sel=sel, out=out[12]);
    Mux(a=a[13], b=b[13], sel=sel, out=out[13]);
    Mux(a=a[14], b=b[14], sel=sel, out=out[14]);
    Mux(a=a[15], b=b[15], sel=sel, out=out[15]);
}

运行结果

Mux4Way16(四选一数据选择器数据位宽16)

真值表

a	b	c	d	sel	out
0000000000000000	0000000000000000	0000000000000000	0000000000000000	00	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	01	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	10	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	11	0000000000000000
0001001000110100	1001100001110110	1010101010101010	0101010101010101	00	0001001000110100
0001001000110100	1001100001110110	1010101010101010	0101010101010101	01	1001100001110110
0001001000110100	1001100001110110	1010101010101010	0101010101010101	10	1010101010101010
0001001000110100	1001100001110110	1010101010101010	0101010101010101	11	0101010101010101

逻辑表达式

Mux4Way16(a,b,c,d,sel)=Mux(Mux(a,b,sel[0]),Mux(c,d,sel[0]), sel[1])
构建思路

使用Mux16, 构建Mux4Way16门
电路图

代码实现

CHIP Mux4Way16 {
    IN a[16], b[16], c[16], d[16], sel[2];
    OUT out[16];

    PARTS:
    Mux16(a=a, b=b, sel=sel[0], out=x1);
    Mux16(a=c, b=d, sel=sel[0], out=x2);
    Mux16(a=x1, b=x2, sel=sel[1], out=out);
}

运行结果

Mux8Way16 (八选一数据选择器数据位宽16)

真值表

a	b	c	d	e	f	g	h	sel	out
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	000	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	001	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	010	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	011	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	100	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	101	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	110	0000000000000000
0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	0000000000000000	111	0000000000000000
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	000	0001001000110100
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	001	0010001101000101
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	010	0011010001010110
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	011	0100010101100111
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	100	0101011001111000
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	101	0110011110001001
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	110	0111100010011010
0001001000110100	0010001101000101	0011010001010110	0100010101100111	0101011001111000	0110011110001001	0111100010011010	1000100110101011	111	1000100110101011

逻辑表达式

Mux8Way16(a,b,c,d,e,f,g,h,sel)=Mux(Mux(Mux(a,b,sel[0]),Mux(c,d,sel[0]), sel[0]), Mux(Mux(Mux(e,f,sel[1]),Mux(g,h,sel[1]), sel[2])
构建思路

使用Mux16, 构建Mux8Way16门
电路图

代码实现

CHIP Mux8Way16 {
    IN a[16], b[16], c[16], d[16],
       e[16], f[16], g[16], h[16],
       sel[3];
    OUT out[16];

    PARTS:
    Mux16(a=a, b=b, sel=sel[0], out=x1);
    Mux16(a=c, b=d, sel=sel[0], out=x2);
    Mux16(a=e, b=f, sel=sel[0], out=x3);
    Mux16(a=g, b=h, sel=sel[0], out=x4);
    Mux16(a=x1, b=x2, sel=sel[1], out=x5);
    Mux16(a=x3, b=x4, sel=sel[1], out=x6);
    Mux16(a=x5, b=x6, sel=sel[2], out=out);
}

运行结果

DMux (多路输出器两路)

真值表

in	sel	a	b
0	0	0	0
0	1	0	0
1	0	1	0
1	1	0	1

逻辑表达式

a=And(Not(sel), in)

b=And(sel, in)
构建思路

使用And/Not, 构建DMux门
电路图

代码实现

CHIP DMux {
    IN in, sel;
    OUT a, b;

    PARTS:
    Not(in=sel, out=Nsel);
    And(a=in, b=Nsel, out=a);
    And(a=in, b=sel, out=b);
}

运行结果

DMux4Way (多路输出器四路)

真值表

in	sel	a	b	c	d
0	00	0	0	0	0
0	01	0	0	0	0
0	10	0	0	0	0
0	11	0	0	0	0
1	00	1	0	0	0
1	01	0	1	0	0
1	10	0	0	1	0
1	11	0	0	0	1

逻辑表达式

DMux4Way(in,sel)=Dmux(Dmux(in,sel[1]), sel[0])
构建思路

使用DMux门电路, 构建DMux4Way门
电路图

代码实现

CHIP DMux4Way {
    IN in, sel[2];
    OUT a, b, c, d;

    PARTS:
    DMux(in=in, sel=sel[0], a=tp1, b=tp2);
    DMux(in=tp1, sel=sel[1], a=a, b=c);
    DMux(in=tp2, sel=sel[1], a=b, b=d);
}

运行结果

DMux8Way (多路输出器八路)

真值表

in	sel	a	b	c	d	e	f	g	h
0	000	0	0	0	0	0	0	0	0
0	001	0	0	0	0	0	0	0	0
0	010	0	0	0	0	0	0	0	0
0	011	0	0	0	0	0	0	0	0
0	100	0	0	0	0	0	0	0	0
0	101	0	0	0	0	0	0	0	0
0	110	0	0	0	0	0	0	0	0
0	111	0	0	0	0	0	0	0	0
1	000	1	0	0	0	0	0	0	0
1	001	0	1	0	0	0	0	0	0
1	010	0	0	1	0	0	0	0	0
1	011	0	0	0	1	0	0	0	0
1	100	0	0	0	0	1	0	0	0
1	101	0	0	0	0	0	1	0	0
1	110	0	0	0	0	0	0	1	0
1	111	0	0	0	0	0	0	0	1

逻辑表达式

Dmux8Way(in,sel)=DMux4Way(Dmux(in, sel), sel[0]=sel[0], sel[1]=sel[1])
构建思路

Dmux8Way(in,sel)=DMux4Way(Dmux(in, sel), sel[0]=sel[0], sel[1]=sel[1])
电路图

代码实现

CHIP DMux8Way {
    IN in, sel[3];
    OUT a, b, c, d, e, f, g, h;

    PARTS:
    DMux(in=in, sel=sel[2], a=outa, b=outb);
    DMux4Way(in=outa, sel[0]=sel[0], sel[1]=sel[1], a=a, b=b, c=c, d=d);
    DMux4Way(in=outb, sel[0]=sel[0], sel[1]=sel[1], a=e, b=f, c=g, d=h);
}

运行结果

练习题

化简下列式子

ACD'+D'=D'(AC+1)=D'
AB'+A'B+A=A(B'+1)+A'B=A+A'B=A+B=(A'B')'

根据逻辑图写出HDL程序

CHIP Test1.2{
    IN a, b;
    OUT out;

    PARTS:
    Nand(a=a, b=b, out=x);
    Nand(a=x, b=x, out=out);
}

画出逻辑电路图

CHIP Test1.3{
    IN a, b;
    OUT out;

    PARTS:
    Not(in=a, out=nota);
    Not(in=b, out=notb);
    Or(a=nota, b=notb, out=AnotB);
    Not(in=AnotB, out=out);
}

考虑一下,这是根据那个表达式写出来的?画出逻辑电路图

CHIP Xor{
    IN a, b;
    OUT out;

    PARTS:
    Nand(a=a, b=b, out=AnandB);
    Or(a=a, b=b, out=AorB);
    And(a=AnandB, b=AorB, out=out);
}

表达式: ab = (ab)' (a+b)=And[Nand(a,b), Or(a,b)]

根据电路图写出HDL语言

CHIP Test1.5{
    IN a, b, c;
    OUT out;

    PARTS:
    Not(in=c, out=n1);
    And(a=n1, b=a, out=a1);
    And(a=b, b=c, out=a2);
    And(a=a, b=b, out=a3);
    Or(a=a2, b=a3, out=o1);
    Or(a=a1, b=o1, out=out);
}

数据的机器层次表示

数值之间的转换

整数十 -> 二(除2取余法, 降幂法)
二转八/二转十六/二转BCD

注意:
BCD码与二进制数之间转换没有直接关系
必须先转换成十进制然后转换成二进制
练习
$$
23=(00010111){2}=(17){16}=(27){8} \
23H=(00100011)B=(35)D=(43)O \
011100011B=(227){10}=(E3)_{16}字和各种字符的编码(ASCII编码)
$$

字和各种字符的编码(ASCII编码)

编码

编码是信息从一种形式或格式转换为另-种形式的过程, 也称为计算机编程语言的代码简称编码.例如: 1234, student , 8421 编码

GBK

GBK码是GB码的扩展字符编码, 对多达2万多的简繁汉字进行了编码, 简体版的Win95和Win98都是使用GBK作系统内码.

ASCII码

采用七位二进制编码, 可以表示128个字符.
bit7作奇倡校验位, 在机器中表示时, 常认为"0", 用一个字长(8位)表示一个ASCII字符.

常用的ASCII字符:
0-9的ASCII码30H-39H
A-Z的ASCII码41H-5AH
a-z的ASCII码61H-7AH

Unicode编码

人们在不断寻找这更好的字符编码方案, 最后的结果就是Unicode诞生了.Unicode其实就是宽字节字符集, 它对每个字符都固定使用两个字节即16位表示, 于是当处理字符时, 不必担心只处理半个字符.

算术逻辑运算

算术运算

二进制数和十六进制数加/减/乘/除, 与十进制数类似

逻辑运算

二进制数运算, 与/或/非/异或, 特点:按位进行

模型机的运算器

运算器用于算术运算和逻辑运算
常见算术运算:加/减/乘/除等.
常见逻辑运算:非/与/或等

进制加/减法

二进制加法

  1001        1111        0000
 +1010       +1100       +1111
-------     -------     -------
  0011        1011        1111

二进制减法

  1001        1111        0000
 -1010       -1100       -1111
-------     -------     -------
  1111        0011       -1111

十六进制加法

  3F39H        00B5H        0000H
 +95FAH       +008FH       +1111H
--------     --------     --------
  D533H        0144H        1111H

十六进制减法

  3F39H        00B5H        0000H
 -95FAH       -008FH       -1111H
--------     --------     --------
  D533H        0026H       -1111H

运算器(ALU)

计算机内数的表示

101

无符号数
带符号数
1. 求补运算
2. 补码
3. 补码的真值计算
4. 用补码表示带符号数的意义
8位/16位数的表示范围
进位/借位/溢出的判断

无符号数

二进制数的各位均表示数值大小, 最高位无符号意义.

例
1111 0000 B= FO H= 15 x 16 = 240D
1001 0001 B= 91 H= 9 x 16 + 1 = 145D
应用场合:
处理的数全是正数时, 如表示地址的数

带符号数

数有正/负→带符号数
通常数的最高位为符号位, 对于字长8位机器数:
D7为符号位: 0表示"+" , 1表示"-". 符号数码化了.
D6~D0为数字位

如:
X=(01011011)2=+91 X=(11011011)2= - 91
连同符号位在一起作为一个数称为机器数,

机器数的数值称为的真值.
如:
N1=+1011011 N2=-1011011为真值
0 101 1011 1 101 1011为机器数

在计算机中符号也用二进制表示

把符号位和数值位一起编码:原码, 反码, 补码.

原码:正数符号位用"0"表示, 负数符号用"1"表示, 这种表示法称为原码.
X=+105 [X]原=0 1101001
X=-105 [X]原=1 1101001
符号数值
反码
1. 正数反码:表示与原码相同,
2. 所谓反码, 就是二进制的各位数码0变为1, 1变为0.
  (最高位"0"表示正, 其余位为数值位.)
3. 负数的反码:表示为负数原码的符号位不变尾数按位取反.
  例:
  [+4]反=0 0000100
  |-4]反=1 11110
  [+127]反= 0 111111
  |-127]反= 1 0000000
  |+0]反 = 0 0000000
  [-0]反=1 1111111
结论
负数反码为符号位跟每位数的反, 0正1负;
反码零有两个编码, +0和-0的编码不同;
反码难以用于加减运算;
反码的表数范围与原码相同.
补码
模的概念
1. 假设两位十进制数计算:
  77-38=39
  77+62=139
  77-38= 77+ 62 =39 ( mod 100)
  由此可以看出, 减38和加62是等价的, 前提是说对模为100是正确的.这个100在数学上称为模数
补码最大的优点就是将减法运算转换成加法运算.
补码表示法

整数:正数的补码与原码一致, 负数的补码为它的原码, 除符号位以外, 各位取反, 最后加1.

小数:正数的补码与原码一致, 负数的补码为它的原码, 除符号位以外, 各位取反, 最后加1.
例题:求-105D的补码
- [105D]补=0110 1001 B=69H
- [105D]补=1001 0110 B=96H
- [105D]补=1001 0110 B + 1=97H

8/16位二进制的范围

8位二进制整数范围

原码/反码:-127-+127
补码/移码:-128-+127
16位二进制整数范围

原码/反码:-32768~+32767
补码/移码:-32768~+32767

溢出及其判断

概念
在定点小数机器中, 数的表示范围为|x|<1.在运算过程中如出现大于1的现象, 称为"溢出".
检测方法
- 单符号法
  溢出逻辑表达式: v=S1'S2'Sc+S1S2Sc'
- 双符号法
  一个符号位只能表示正/负两种情况, 当产生溢出时, 符号位的含义就会发生混乱.如果将符号位扩充为两位(Sf1/Sf2),其所能表示的信息量将随之扩大, 既能判别是否溢出, 又能指出结果的符号.
  双符号位法也称为"变形补或 "模4补码"
  变形补码定义:
  $$
  |x|补=\left{\begin{matrix}
  x & 0\le x<2\
  4+x & -2\le x<0 (mod 4)
  \end{matrix}\right.
  $$

采用变形补码后数的表示:

任何小于1的正数:两个符号位都是 "0", 即.x.2...x.;.
任何大于-1的负数:两个符号位都是"1", 即1.x.x...x
模4补码加法公式:|x|补+|y|补=|x+y|补 (mod 4)
两数变形补码之和等于两数和的变形补码, 要求:
两个符号位都看做数码一样参加运算;
= 两数进行以4为模的加法, 即最高符号位上产生的进位要丢掉
双符号位的含义如下

Sf1Sf2 = 00 结果为正数, 无溢出
01 结果正溢
10 结果负溢
11 结果为负数

即:结果的两个符号位的代码不一致时, 表示溢出;
两个符号位的代码--致时表示没有溢出..
不管溢出与否, 最高符号位永远表示结果的正确符号.

溢出逻辑表达式为:
$$
V=Sf1\oplus Sf2
$$

中Sg和Sq分别为最高符号位和第二符号位, 此逻辑表达式可用异或门实现.

104
105

利用进位制的判别法

从上面例中看到:
当最高有效位有进位而符号1无进位时,产生上溢;
当最高有效位无进位而符号位有进位时,产生下溢.
(简单地说是正数相加为负数或负数相加为正数则产生溢出)
故溢出逻辑表达式为:
$$
V=Cf\oplus C0
$$

其中C为符号位产生的进位, C.为最高有效位产生的进位.
此逻辑表达式也可用异或门实现.

运算器设计实现

HalfAdder (半加器)

用来进行两位加法

进行二进制加法的第一步就是要能够对两个二进制位进行相加. 我们把结果的LSB位称为sum, MSB位称为carry

真值表

a	b	sum	carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

逻辑表达式

HalfAdder(a, b)=Xor(a,b);

HalfAdder(a, b)=And(a,b);
构建思路

使用And/Xor门电路, 构建HalfAdder
电路图

代码实现

CHIP HalfAdder {
    IN a, b;
    OUT sum,
        carry;

    PARTS:
    Xor(a=a, b=b, out=sum);
    And(a=a, b=b, out=carry);
}

运算结果

FullAdder (全加器)

用来进行三位加法

真值表

a	b	c	sum	carry
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

逻辑表达式

FullAdder(a, b, c)=Or(HalfAdder(a,b), HalfAdder(HalfAdder(a,b), c))
构建思路

使用两个HalfAdder, 构建FullAdder
电路图

代码实现

CHIP FullAdder {
    IN a, b, c;
    OUT sum,carry;

    PARTS:
    HalfAdder(a=a, b=b, sum=sumA, carry=carryA);
    HalfAdder(a=sumA, b=c, sum=sum, carry=carryB);
    Or(a=carryA, b=carryB, out=carry);
}

运算结果

Add16 (16位加法器)

存储器和寄存器电路用n-位的形式来表示整数, n可以是16/32/64等等--这依赖与所在的计算机平台.

真值表

a	b	out
0000000000000000	0000000000000000	0000000000000000
0000000000000000	1111111111111111	1111111111111111
1111111111111111	1111111111111111	1111111111111110
1010101010101010	0101010101010101	1111111111111111
0011110011000011	0000111111110000	0100110010110011
0001001000110100	1001100001110110	1010101010101010

逻辑表达式

Add16(a, b)=FullAdder(a[0...15], b[0...15], c[false...carryo], sum[0...15], carry=carry(A...O))
构建思路

使用FullAdder, 构建Add16
电路图

代码实现

CHIP Add16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    FullAdder(a=a[0], b=b[0], c=false, sum=out[0], carry=carryA);
    FullAdder(a=a[1], b=b[1], c=carryA, sum=out[1], carry=carryB);
    FullAdder(a=a[2], b=b[2], c=carryB, sum=out[2], carry=carryC);
    FullAdder(a=a[3], b=b[3], c=carryC, sum=out[3], carry=carryD);
    FullAdder(a=a[4], b=b[4], c=carryD, sum=out[4], carry=carryE);
    FullAdder(a=a[5], b=b[5], c=carryE, sum=out[5], carry=carryF);
    FullAdder(a=a[6], b=b[6], c=carryF, sum=out[6], carry=carryG);
    FullAdder(a=a[7], b=b[7], c=carryG, sum=out[7], carry=carryH);
    FullAdder(a=a[8], b=b[8], c=carryH, sum=out[8], carry=carryI);
    FullAdder(a=a[9], b=b[9], c=carryI, sum=out[9], carry=carryJ);
    FullAdder(a=a[10], b=b[10], c=carryJ, sum=out[10], carry=carryK);
    FullAdder(a=a[11], b=b[11], c=carryK, sum=out[11], carry=carryL);
    FullAdder(a=a[12], b=b[12], c=carryL, sum=out[12], carry=carryM);
    FullAdder(a=a[13], b=b[13], c=carryM, sum=out[13], carry=carryN);
    FullAdder(a=a[14], b=b[14], c=carryN, sum=out[14], carry=carryO);
    FullAdder(a=a[15], b=b[15], c=carryO, sum=out[15], carry=carry);
}

运算结果

Inc16 (递增器)

专门构建一个"对指定数字加1"的电路, 这样做会带来很多便利.

真值表

in	out
0000000000000000	0000000000000001
1111111111111111	0000000000000000
0000000000000101	0000000000000110
1111111111111011	1111111111111100

逻辑表达式

Inc16(a, b)=Add16(a, b)
构建思路

使用Add16, 构建Inc16
代码实现

CHIP Inc16 {
    IN in[16];
    OUT out[16];

    PARTS:
    Add16(a=in, b[0]=true, out=out);
}

运算结果

ALU

ALU将成为Hack计算机平台的核心部分. 同时, ALU的设计原则是相当通用. 不经如此, 我们的ALU体系结构通过最小的逻辑单元来实现大量功能, 从这点看, 他是逻辑设计中高效的优良设计的典范.

真值表

x	y	zx	nx	zy	ny	f	no	out	zr	ng
0000000000000000	1111111111111111	1	0	1	0	1	0	0000000000000000	1	0
0000000000000000	1111111111111111	1	1	1	1	1	1	0000000000000001	0	0
0000000000000000	1111111111111111	1	1	1	0	1	0	1111111111111111	0	1
0000000000000000	1111111111111111	0	0	1	1	0	0	0000000000000000	1	0
0000000000000000	1111111111111111	1	1	0	0	0	0	1111111111111111	0	1
0000000000000000	1111111111111111	0	0	1	1	0	1	1111111111111111	0	1
0000000000000000	1111111111111111	1	1	0	0	0	1	0000000000000000	1	0
0000000000000000	1111111111111111	0	0	1	1	1	1	0000000000000000	1	0
0000000000000000	1111111111111111	1	1	0	0	1	1	0000000000000001	0	0
0000000000000000	1111111111111111	0	1	1	1	1	1	0000000000000001	0	0
0000000000000000	1111111111111111	1	1	0	1	1	1	0000000000000000	1	0
0000000000000000	1111111111111111	0	0	1	1	1	0	1111111111111111	0	1
0000000000000000	1111111111111111	1	1	0	0	1	0	1111111111111110	0	1
0000000000000000	1111111111111111	0	0	0	0	1	0	1111111111111111	0	1
0000000000000000	1111111111111111	0	1	0	0	1	1	0000000000000001	0	0
0000000000000000	1111111111111111	0	0	0	1	1	1	1111111111111111	0	1
0000000000000000	1111111111111111	0	0	0	0	0	0	0000000000000000	1	0
0000000000000000	1111111111111111	0	1	0	1	0	1	1111111111111111	0	1
0000000000010001	0000000000000011	1	0	1	0	1	0	0000000000000000	1	0
0000000000010001	0000000000000011	1	1	1	1	1	1	0000000000000001	0	0
0000000000010001	0000000000000011	1	1	1	0	1	0	1111111111111111	0	1
0000000000010001	0000000000000011	0	0	1	1	0	0	0000000000010001	0	0
0000000000010001	0000000000000011	1	1	0	0	0	0	0000000000000011	0	0
0000000000010001	0000000000000011	0	0	1	1	0	1	1111111111101110	0	1
0000000000010001	0000000000000011	1	1	0	0	0	1	1111111111111100	0	1
0000000000010001	0000000000000011	0	0	1	1	1	1	1111111111101111	0	1
0000000000010001	0000000000000011	1	1	0	0	1	1	1111111111111101	0	1
0000000000010001	0000000000000011	0	1	1	1	1	1	0000000000010010	0	0
0000000000010001	0000000000000011	1	1	0	1	1	1	0000000000000100	0	0
0000000000010001	0000000000000011	0	0	1	1	1	0	0000000000010000	0	0
0000000000010001	0000000000000011	1	1	0	0	1	0	0000000000000010	0	0
0000000000010001	0000000000000011	0	0	0	0	1	0	0000000000010100	0	0
0000000000010001	0000000000000011	0	1	0	0	1	1	0000000000001110	0	0
0000000000010001	0000000000000011	0	0	0	1	1	1	1111111111110010	0	1
0000000000010001	0000000000000011	0	0	0	0	0	0	0000000000000001	0	0
0000000000010001	0000000000000011	0	1	0	1	0	1	0000000000010011	0	0

逻辑表达式

Not(Or(Or8Way(Mux16(Mux16(And16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), Add16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), sel=f), Not(Mux16(And16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), Add16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), sel=f)), sel=no, out[0..7])), Or8Way( Mux16(Mux16(And16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), Add16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), sel=f), Not(Mux16(And16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), Add16(Mux16(Mux16(x, false, zx), Not(Mux16(x, false, zx))), Mux16(Mux16(y, false, zy), Not(Mux16(y, false, zy)))), sel=f)), sel=no, out[8..15]))))
构建思路

用Mux16/Add16/And16/Not/Or8Way, 构建ALU
电路图

实现代码

CHIP ALU {
    IN
        x[16], y[16],  // 16-bit inputs
        zx, // zero the x input?
        nx, // negate the x input?
        zy, // zero the y input?
        ny, // negate the y input?
        f,  // compute out = x + y (if 1) or x & y (if 0)
        no; // negate the out output?

    OUT
        out[16], // 16-bit output
        zr, // 1 if (out == 0), 0 otherwise
        ng; // 1 if (out < 0),  0 otherwise

    PARTS:

    Mux16(a=x, b[0]=false, sel=zx, out=outX);
    Not16(in=outX, out=outNotX);
    Mux16(a=outX, b=outNotX, sel=nx, out=out2X);

    Mux16(a=y, b[0]=false, sel=zy, out=outY);
    Not16(in=outY, out=outNotY);
    Mux16(a=outY, b=outNotY, sel=ny, out=out2Y);

    And16(a=out2X, b=out2Y, out=outAnd16);
    Add16(a=out2X, b=out2Y, out=outAdd16);

    Mux16(a=outAnd16, b=outAdd16, sel=f, out=out1);

    Not16(in=out1, out=out1N);


    Mux16(a=out1, b=out1N, sel=no, out=out, out[0..7]=zrtest1, out[8..15]=zrtest2, out[15]=ng);

    Or8Way(in=zrtest1, out=outOr1);
    Or8Way(in=zrtest2, out=outOr2);

    Or(a=outOr1, b=outOr2, out=outOrPtr);

    Not(in=outOrPtr, out=zr);
}

运算结果

超前进位加法器

四位超前进位加法器

真值表


a	b	cin	s	cout
0000	0000	0	0000	0
0000	0000	1	0001	0
0000	1111	0	1111	0
0000	1111	1	0000	1
1111	1111	0	1110	1
1111	1111	1	1111	1
1010	0101	0	1111	0
1010	0101	1	0000	1
0011	1100	0	1111	0
0011	1100	1	0000	1
1001	0110	0	1111	0
1001	0110	1	0000	1

逻辑表达

电路图

代码实现

CHIP Add4 {
    IN a[4], b[4], cin;
    OUT s[4], cout;

    PARTS:
    HalfAdder(a=a[0], b=b[0], sum=P0, carry=G0);
    HalfAdder(a=a[1], b=b[1], sum=P1, carry=G1);
    HalfAdder(a=a[2], b=b[2], sum=P2, carry=G2);
    HalfAdder(a=a[3], b=b[3], sum=P3, carry=G3);

    And5(a=cin, b=P0, c=P1, d=P2, e=P3, out=a5);
    And4(a=G0, b=P1, c=P2, d=P3, out=a4);
    And3(a=G1, b=P2, c=P3, out=a3);
    And(a=G2, b=P3, out=a2);

    Or5(a=G3, b=a2, c=a3, d=a4, e=a5, out=cout);


    And4(a=P2, b=P1, c=P0, d=cin, out=b3);
    And3(a=P2, b=P1, c=G0, out=b2);
    And(a=P2, b=G1, out=b1);

    Or4(a=G2, b=b1, c=b2, d=b3, out=C3);


    And3(a=P1, b=P0, c=cin, out=c2);
    And(a=P1, b=G0, out=c1);

    Or3(a=G1, b=c1, c=c2, out=C2);


    And(a=P0, b=cin, out=d1);
    Or(a=G0, b=d1, out=C1);


    Xor(a=P0, b=cin, out=s[0]);
    Xor(a=P1, b=C1, out=s[1]);
    Xor(a=P2, b=C2, out=s[2]);
    Xor(a=P3, b=C3, out=s[3]);
}

运算结果

十六位超前进位加法器

真值表

a	b	out
0000000000000000	0000000000000000	0000000000000000
0000000000000000	1111111111111111	1111111111111111
1111111111111111	1111111111111111	1111111111111110
1010101010101010	0101010101010101	1111111111111111
0011110011000011	0000111111110000	0100110010110011
0001001000110100	1001100001110110	1010101010101010

电路图

代码实现

CHIP Add16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    Add4(a=a[0..3], b=b[0..3], cin=false, s=out[0..3], cout=cout1);
    Add4(a=a[4..7], b=b[4..7], cin=cout1, s=out[4..7], cout=cout2);
    Add4(a=a[8..11], b=b[8..11], cin=cout2, s=out[8..11], cout=cout3);
    Add4(a=a[12..15], b=b[12..15], cin=cout3, s=out[12..15], cout=cout);
}

运算结果

时序逻辑

背景

在前两章里面构建的所有的布尔芯片和算术芯片都是组合芯片(Combinatorial Chips). 组合芯片计算那些"输出结果因依赖于其输入变量的排列组合"的函数. 这些相关的简单芯片提供很多重要信息的处理能力(像ALU一样), 但是他们却不能维持自身状态. 计算机不能要能计算值, 而且还需要存取数据, 因而这些芯片必须配备记忆单元(Memory Elements)来保存数据, 这些记忆单元是由时序芯片(Sequential Chips)组成.这些记忆单元的实现是复杂的过程, 设计了同步/时钟/反馈回路. 大部分能够被封装到触发器(Flip-Flop)的底层时序门中.

时钟(Clock) 在大多数计算机里, 时间的流逝是用主时钟(master clock)来表示的, 它提供连续的交变信号序列.其精确的硬件实现通常基于振荡器(oscillator), 其在两个信号值0-1,或称"低电平-高电平(ow-nigh, tick-tock)" 之间交替变化..

触发器(Flip-Flops) 计算机里最基本的时序单元是称为触发器的设备.

真值表

D	Qn+1
0	0
1	1

寄存器(Registers) 寄存器是具有记忆功能的设备, 它能够"储存"或称"记忆"

D触发器电路(DFF)

Data-Flip-Flop

注意到电路符号上的白色小三⻆了吗, 那说明它是时钟驱动的芯片."时钟"在该系列实验中的含义如下:

它的一个周期包含 tick(低电平) 和 tock(高电平) 两个阶段.在硬件仿真器里, 在 tick 阶段时序逻辑类芯片的输入被读取并影响到其存储单元, 在 tock 阶段结束后(一个周期结束)输出值反映新的变化.所以在 DFF 电路符号下方的 out(t) = in(t-1) 应理解为 DFF 的当前输出是上一周期的输入, 或者说从 tock 到 tick 的那个下降沿是时序
逻辑电路输出变化的时刻.

设计时序芯片

二地址指令操作数物理位置的三种形式

寄存器--寄存器型(RR型)；
寄存器--存储器型指令(RS型)；
存储器--存储器型(SS型).

Bit 1⽐特寄存器

1比特位寄存器, 可以称为比特(Bit), 或二进制单元(binary cll),用来存储信息的1个比特位(0或1).芯片接口包括:一个输入管脚(它传输一个比特数据);一个能够使该寄存器进行写操作的Load管脚; 一个输出管脚(用来输出寄存器的当前状态).二进制单元的接口图和API如下所示:

真值表

time	in	load	out
0+	0	0	0
1	0	0	0
1+	0	1	0
2	0	1	0
2+	1	0	0
3	1	0	0
3+	1	1	0
4	1	1	1
4+	0	0	1
5	0	0	1
5+	1	0	1
6	1	0	1
6+	0	1	1
7	0	1	0
7+	1	1	0
8	1	1	1
8+	0	0	1
9	0	0	1
9+	0	0	1
10	0	0	1
10+	0	0	1
11	0	0	1
11+	0	0	1
12	0	0	1
12+	0	0	1
13	0	0	1
13+	0	0	1
14	0	0	1
14+	0	0	1
15	0	0	1
15+	0	0	1
16	0	0	1
16+	0	0	1
17	0	0	1
17+	0	0	1
18	0	0	1
18+	0	0	1
19	0	0	1
19+	0	0	1
20	0	0	1
20+	0	0	1
21	0	0	1
21+	0	0	1
22	0	0	1
22+	0	0	1
23	0	0	1
23+	0	0	1
24	0	0	1
24+	0	0	1
25	0	0	1
25+	0	0	1
26	0	0	1
26+	0	0	1
27	0	0	1
27+	0	0	1
28	0	0	1
28+	0	0	1
29	0	0	1
29+	0	0	1
30	0	0	1
30+	0	0	1
31	0	0	1
31+	0	0	1
32	0	0	1
32+	0	0	1
33	0	0	1
33+	0	0	1
34	0	0	1
34+	0	0	1
35	0	0	1
35+	0	0	1
36	0	0	1
36+	0	0	1
37	0	0	1
37+	0	0	1
38	0	0	1
38+	0	0	1
39	0	0	1
39+	0	0	1
40	0	0	1
40+	0	0	1
41	0	0	1
41+	0	0	1
42	0	0	1
42+	0	0	1
43	0	0	1
43+	0	0	1
44	0	0	1
44+	0	0	1
45	0	0	1
45+	0	0	1
46	0	0	1
46+	0	0	1
47	0	0	1
47+	0	0	1
48	0	0	1
48+	0	0	1
49	0	0	1
49+	0	0	1
50	0	0	1
50+	0	0	1
51	0	0	1
51+	0	0	1
52	0	0	1
52+	0	0	1
53	0	0	1
53+	0	0	1
54	0	0	1
54+	0	0	1
55	0	0	1
55+	0	0	1
56	0	0	1
56+	0	0	1
57	0	0	1
57+	0	1	1
58	0	1	0
58+	1	0	0
59	1	0	0
59+	1	0	0
60	1	0	0
60+	1	0	0
61	1	0	0
61+	1	0	0
62	1	0	0
62+	1	0	0
63	1	0	0
63+	1	0	0
64	1	0	0
64+	1	0	0
65	1	0	0
65+	1	0	0
66	1	0	0
66+	1	0	0
67	1	0	0
67+	1	0	0
68	1	0	0
68+	1	0	0
69	1	0	0
69+	1	0	0
70	1	0	0
70+	1	0	0
71	1	0	0
71+	1	0	0
72	1	0	0
72+	1	0	0
73	1	0	0
73+	1	0	0
74	1	0	0
74+	1	0	0
75	1	0	0
75+	1	0	0
76	1	0	0
76+	1	0	0
77	1	0	0
77+	1	0	0
78	1	0	0
78+	1	0	0
79	1	0	0
79+	1	0	0
80	1	0	0
80+	1	0	0
81	1	0	0
81+	1	0	0
82	1	0	0
82+	1	0	0
83	1	0	0
83+	1	0	0
84	1	0	0
84+	1	0	0
85	1	0	0
85+	1	0	0
86	1	0	0
86+	1	0	0
87	1	0	0
87+	1	0	0
88	1	0	0
88+	1	0	0
89	1	0	0
89+	1	0	0
90	1	0	0
90+	1	0	0
91	1	0	0
91+	1	0	0
92	1	0	0
92+	1	0	0
93	1	0	0
93+	1	0	0
94	1	0	0
94+	1	0	0
95	1	0	0
95+	1	0	0
96	1	0	0
96+	1	0	0
97	1	0	0
97+	1	0	0
98	1	0	0
98+	1	0	0
99	1	0	0
99+	1	0	0
100	1	0	0
100+	1	0	0
101	1	0	0
101+	1	0	0
102	1	0	0
102+	1	0	0
103	1	0	0
103+	1	0	0
104	1	0	0
104+	1	0	0
105	1	0	0
105+	1	0	0
106	1	0	0
106+	1	0	0
107	1	0	0

电路图
代码实现

CHIP Bit {
    IN in, load;
    OUT out;

    PARTS:
    Mux(a = out1, b = in, sel = load, out = muxo);
    DFF(in = muxo, out = out1, out = out);
}

运行结果

Register 16⽐特寄存器

比特和寄存器芯片的读/写行为几乎是一样的:
读(Read):要读取寄存器的内容, 只需获取它的输出.
写(Write): 要将新数据值d写入寄存器, 只需将d置于in输入管脚, 并将load输入管脚的值设为1.这样, 在下一个时钟周期内, 寄存器被赋予了新的数据值, 它的输出变成了d.

真值表

time	in	load	out
0+	0	0	0
1	0	0	0
1+	0	1	0
2	0	1	0
2+	-32123	0	0
3	-32123	0	0
3+	11111	0	0
4	11111	0	0
4+	-32123	1	0
5	-32123	1	-32123
5+	-32123	1	-32123
6	-32123	1	-32123
6+	-32123	0	-32123
7	-32123	0	-32123
7+	12345	1	-32123
8	12345	1	12345
8+	0	0	12345
9	0	0	12345
9+	0	1	12345
10	0	1	0
10+	1	0	0
11	1	0	0
11+	1	1	0
12	1	1	1
12+	2	0	1
13	2	0	1
13+	2	1	1
14	2	1	2
14+	4	0	2
15	4	0	2
15+	4	1	2
16	4	1	4
16+	8	0	4
17	8	0	4
17+	8	1	4
18	8	1	8
18+	16	0	8
19	16	0	8
19+	16	1	8
20	16	1	16
20+	32	0	16
21	32	0	16
21+	32	1	16
22	32	1	32
22+	64	0	32
23	64	0	32
23+	64	1	32
24	64	1	64
24+	128	0	64
25	128	0	64
25+	128	1	64
26	128	1	128
26+	256	0	128
27	256	0	128
27+	256	1	128
28	256	1	256
28+	512	0	256
29	512	0	256
29+	512	1	256
30	512	1	512
30+	1024	0	512
31	1024	0	512
31+	1024	1	512
32	1024	1	1024
32+	2048	0	1024
33	2048	0	1024
33+	2048	1	1024
34	2048	1	2048
34+	4096	0	2048
35	4096	0	2048
35+	4096	1	2048
36	4096	1	4096
36+	8192	0	4096
37	8192	0	4096
37+	8192	1	4096
38	8192	1	8192
38+	16384	0	8192
39	16384	0	8192
39+	16384	1	8192
40	16384	1	16384
40+	-32768	0	16384
41	-32768	0	16384
41+	-32768	1	16384
42	-32768	1	-32768
42+	-2	0	-32768
43	-2	0	-32768
43+	-2	1	-32768
44	-2	1	-2
44+	-3	0	-2
45	-3	0	-2
45+	-3	1	-2
46	-3	1	-3
46+	-5	0	-3
47	-5	0	-3
47+	-5	1	-3
48	-5	1	-5
48+	-9	0	-5
49	-9	0	-5
49+	-9	1	-5
50	-9	1	-9
50+	-17	0	-9
51	-17	0	-9
51+	-17	1	-9
52	-17	1	-17
52+	-33	0	-17
53	-33	0	-17
53+	-33	1	-17
54	-33	1	-33
54+	-65	0	-33
55	-65	0	-33
55+	-65	1	-33
56	-65	1	-65
56+	-129	0	-65
57	-129	0	-65
57+	-129	1	-65
58	-129	1	-129
58+	-257	0	-129
59	-257	0	-129
59+	-257	1	-129
60	-257	1	-257
60+	-513	0	-257
61	-513	0	-257
61+	-513	1	-257
62	-513	1	-513
62+	-1025	0	-513
63	-1025	0	-513
63+	-1025	1	-513
64	-1025	1	-1025
64+	-2049	0	-1025
65	-2049	0	-1025
65+	-2049	1	-1025
66	-2049	1	-2049
66+	-4097	0	-2049
67	-4097	0	-2049
67+	-4097	1	-2049
68	-4097	1	-4097
68+	-8193	0	-4097
69	-8193	0	-4097
69+	-8193	1	-4097
70	-8193	1	-8193
70+	-16385	0	-8193
71	-16385	0	-8193
71+	-16385	1	-8193
72	-16385	1	-16385
72+	32767	0	-16385
73	32767	0	-16385
73+	32767	1	-16385
74	32767	1	32767

电路图

代码实现

CHIP Register {
    IN in[16], load;
    OUT out[16];

    PARTS:
    Bit(in = in[0], load = load, out = out[0]);
    Bit(in = in[1], load = load, out = out[1]);
    Bit(in = in[2], load = load, out = out[2]);
    Bit(in = in[3], load = load, out = out[3]);
    Bit(in = in[4], load = load, out = out[4]);
    Bit(in = in[5], load = load, out = out[5]);
    Bit(in = in[6], load = load, out = out[6]);
    Bit(in = in[7], load = load, out = out[7]);
    Bit(in = in[8], load = load, out = out[8]);
    Bit(in = in[9], load = load, out = out[9]);
    Bit(in = in[10], load = load, out = out[10]);
    Bit(in = in[11], load = load, out = out[11]);
    Bit(in = in[12], load = load, out = out[12]);
    Bit(in = in[13], load = load, out = out[13]);
    Bit(in = in[14], load = load, out = out[14]);
    Bit(in = in[15], load = load, out = out[15]);
}

运行结果

RAM8 8-register 存储器

可进行直接访问的记忆单元也称为RAM,是由n个w~位寄存器组成的阵列,配有直接访问电路(direct access circuitry). 寄存器的个数(n)和每个寄存器的宽度(w)分别称为内存的尺寸(size) 和宽度(width). 我们将开始构建一组这样的存储体系, 都是16位宽, 但是大小不同: RAM8/ RAM64/ RAM512/RAM4K 和RAM16K.所有这些内存芯片都有相同的API

真值表

time	in	load	address	out
0+	0	0	0	0
1	0	0	0	0
1+	0	1	0	0
2	0	1	0	0
2+	11111	0	0	0
3	11111	0	0	0
3+	11111	1	1	0
4	11111	1	1	11111
4+	11111	0	0	0
5	11111	0	0	0
5+	3333	0	3	0
6	3333	0	3	0
6+	3333	1	3	0
7	3333	1	3	3333
7+	3333	0	3	3333
8	3333	0	3	3333
8	3333	0	1	11111
8+	7777	0	1	11111
9	7777	0	1	11111
9+	7777	1	7	0
10	7777	1	7	7777
10+	7777	0	7	7777
11	7777	0	7	7777
11	7777	0	3	3333
11	7777	0	7	7777
11+	7777	0	0	0
12	7777	0	0	0
12	7777	0	1	11111
12	7777	0	2	0
12	7777	0	3	3333
12	7777	0	4	0
12	7777	0	5	0
12	7777	0	6	0
12	7777	0	7	7777
12+	21845	1	0	0
13	21845	1	0	21845
13+	21845	1	1	11111
14	21845	1	1	21845
14+	21845	1	2	0
15	21845	1	2	21845
15+	21845	1	3	3333
16	21845	1	3	21845
16+	21845	1	4	0
17	21845	1	4	21845
17+	21845	1	5	0
18	21845	1	5	21845
18+	21845	1	6	0
19	21845	1	6	21845
19+	21845	1	7	7777
20	21845	1	7	21845
20+	21845	0	0	21845
21	21845	0	0	21845
21	21845	0	1	21845
21	21845	0	2	21845
21	21845	0	3	21845
21	21845	0	4	21845
21	21845	0	5	21845
21	21845	0	6	21845
21	21845	0	7	21845
21+	-21846	1	0	21845
22	-21846	1	0	-21846
22+	-21846	0	0	-21846
23	-21846	0	0	-21846
23	-21846	0	1	21845
23	-21846	0	2	21845
23	-21846	0	3	21845
23	-21846	0	4	21845
23	-21846	0	5	21845
23	-21846	0	6	21845
23	-21846	0	7	21845
23+	21845	1	0	-21846
24	21845	1	0	21845
24+	-21846	1	1	21845
25	-21846	1	1	-21846
25+	-21846	0	0	21845
26	-21846	0	0	21845
26	-21846	0	1	-21846
26	-21846	0	2	21845
26	-21846	0	3	21845
26	-21846	0	4	21845
26	-21846	0	5	21845
26	-21846	0	6	21845
26	-21846	0	7	21845
26+	21845	1	1	-21846
27	21845	1	1	21845
27+	-21846	1	2	21845
28	-21846	1	2	-21846
28+	-21846	0	0	21845
29	-21846	0	0	21845
29	-21846	0	1	21845
29	-21846	0	2	-21846
29	-21846	0	3	21845
29	-21846	0	4	21845
29	-21846	0	5	21845
29	-21846	0	6	21845
29	-21846	0	7	21845
29+	21845	1	2	-21846
30	21845	1	2	21845
30+	-21846	1	3	21845
31	-21846	1	3	-21846
31+	-21846	0	0	21845
32	-21846	0	0	21845
32	-21846	0	1	21845
32	-21846	0	2	21845
32	-21846	0	3	-21846
32	-21846	0	4	21845
32	-21846	0	5	21845
32	-21846	0	6	21845
32	-21846	0	7	21845
32+	21845	1	3	-21846
33	21845	1	3	21845
33+	-21846	1	4	21845
34	-21846	1	4	-21846
34+	-21846	0	0	21845
35	-21846	0	0	21845
35	-21846	0	1	21845
35	-21846	0	2	21845
35	-21846	0	3	21845
35	-21846	0	4	-21846
35	-21846	0	5	21845
35	-21846	0	6	21845
35	-21846	0	7	21845
35+	21845	1	4	-21846
36	21845	1	4	21845
36+	-21846	1	5	21845
37	-21846	1	5	-21846
37+	-21846	0	0	21845
38	-21846	0	0	21845
38	-21846	0	1	21845
38	-21846	0	2	21845
38	-21846	0	3	21845
38	-21846	0	4	21845
38	-21846	0	5	-21846
38	-21846	0	6	21845
38	-21846	0	7	21845
38+	21845	1	5	-21846
39	21845	1	5	21845
39+	-21846	1	6	21845
40	-21846	1	6	-21846
40+	-21846	0	0	21845
41	-21846	0	0	21845
41	-21846	0	1	21845
41	-21846	0	2	21845
41	-21846	0	3	21845
41	-21846	0	4	21845
41	-21846	0	5	21845
41	-21846	0	6	-21846
41	-21846	0	7	21845
41+	21845	1	6	-21846
42	21845	1	6	21845
42+	-21846	1	7	21845
43	-21846	1	7	-21846
43+	-21846	0	0	21845
44	-21846	0	0	21845
44	-21846	0	1	21845
44	-21846	0	2	21845
44	-21846	0	3	21845
44	-21846	0	4	21845
44	-21846	0	5	21845
44	-21846	0	6	21845
44	-21846	0	7	-21846
44+	21845	1	7	-21846
45	21845	1	7	21845
45+	21845	0	0	21845
46	21845	0	0	21845
46	21845	0	1	21845
46	21845	0	2	21845
46	21845	0	3	21845
46	21845	0	4	21845
46	21845	0	5	21845
46	21845	0	6	21845
46	21845	0	7	21845

电路图

代码实现

CHIP RAM8 {
    IN in[16], load, address[3];
    OUT out[16];

    PARTS:
    DMux8Way(in = load, sel = address,a = a0,
    b = a1, c = a2, d = a3,e = a4, f = a5,g = a6, h = a7);
    Register(in = in, load = a0, out = out0);
    Register(in = in, load = a1, out = out1);
    Register(in = in, load = a2, out = out2);
    Register(in = in, load = a3, out = out3);
    Register(in = in, load = a4, out = out4);
    Register(in = in, load = a5, out = out5);
    Register(in = in, load = a6, out = out6);
    Register(in = in, load = a7, out = out7);
    Mux8Way16(a = out0, b = out1, c = out2,
    d = out3, e = out4, f = out5, g = out6,
    h = out7, sel = address[0..2], out = out);
}

运行结果

RAM64 64-register 存储器

真值表

time	in	load	address	out
0+	0	0	0	0
1	0	0	0	0
1+	0	1	0	0
2	0	1	0	0
2+	1313	0	0	0
3	1313	0	0	0
3+	1313	1	13	0
4	1313	1	13	1313
4+	1313	0	0	0
5	1313	0	0	0
5+	4747	0	47	0
6	4747	0	47	0
6+	4747	1	47	0
7	4747	1	47	4747
7+	4747	0	47	4747
8	4747	0	47	4747
8	4747	0	13	1313
8+	6363	0	13	1313
9	6363	0	13	1313
9+	6363	1	63	0
10	6363	1	63	6363
10+	6363	0	63	6363
11	6363	0	63	6363
11	6363	0	47	4747
11	6363	0	63	6363
11+	6363	0	40	0
12	6363	0	40	0
12	6363	0	41	0
12	6363	0	42	0
12	6363	0	43	0
12	6363	0	44	0
12	6363	0	45	0
12	6363	0	46	0
12	6363	0	47	4747
12+	21845	1	40	0
13	21845	1	40	21845
13+	21845	1	41	0
14	21845	1	41	21845
14+	21845	1	42	0
15	21845	1	42	21845
15+	21845	1	43	0
16	21845	1	43	21845
16+	21845	1	44	0
17	21845	1	44	21845
17+	21845	1	45	0
18	21845	1	45	21845
18+	21845	1	46	0
19	21845	1	46	21845
19+	21845	1	47	4747
20	21845	1	47	21845
20+	21845	0	40	21845
21	21845	0	40	21845
21	21845	0	41	21845
21	21845	0	42	21845
21	21845	0	43	21845
21	21845	0	44	21845
21	21845	0	45	21845
21	21845	0	46	21845
21	21845	0	47	21845
21+	-21846	1	40	21845
22	-21846	1	40	-21846
22+	-21846	0	40	-21846
23	-21846	0	40	-21846
23	-21846	0	41	21845
23	-21846	0	42	21845
23	-21846	0	43	21845
23	-21846	0	44	21845
23	-21846	0	45	21845
23	-21846	0	46	21845
23	-21846	0	47	21845
23+	21845	1	40	-21846
24	21845	1	40	21845
24+	-21846	1	41	21845
25	-21846	1	41	-21846
25+	-21846	0	40	21845
26	-21846	0	40	21845
26	-21846	0	41	-21846
26	-21846	0	42	21845
26	-21846	0	43	21845
26	-21846	0	44	21845
26	-21846	0	45	21845
26	-21846	0	46	21845
26	-21846	0	47	21845
26+	21845	1	41	-21846
27	21845	1	41	21845
27+	-21846	1	42	21845
28	-21846	1	42	-21846
28+	-21846	0	40	21845
29	-21846	0	40	21845
29	-21846	0	41	21845
29	-21846	0	42	-21846
29	-21846	0	43	21845
29	-21846	0	44	21845
29	-21846	0	45	21845
29	-21846	0	46	21845
29	-21846	0	47	21845
29+	21845	1	42	-21846
30	21845	1	42	21845
30+	-21846	1	43	21845
31	-21846	1	43	-21846
31+	-21846	0	40	21845
32	-21846	0	40	21845
32	-21846	0	41	21845
32	-21846	0	42	21845
32	-21846	0	43	-21846
32	-21846	0	44	21845
32	-21846	0	45	21845
32	-21846	0	46	21845
32	-21846	0	47	21845
32+	21845	1	43	-21846
33	21845	1	43	21845
33+	-21846	1	44	21845
34	-21846	1	44	-21846
34+	-21846	0	40	21845
35	-21846	0	40	21845
35	-21846	0	41	21845
35	-21846	0	42	21845
35	-21846	0	43	21845
35	-21846	0	44	-21846
35	-21846	0	45	21845
35	-21846	0	46	21845
35	-21846	0	47	21845
35+	21845	1	44	-21846
36	21845	1	44	21845
36+	-21846	1	45	21845
37	-21846	1	45	-21846
37+	-21846	0	40	21845
38	-21846	0	40	21845
38	-21846	0	41	21845
38	-21846	0	42	21845
38	-21846	0	43	21845
38	-21846	0	44	21845
38	-21846	0	45	-21846
38	-21846	0	46	21845
38	-21846	0	47	21845
38+	21845	1	45	-21846
39	21845	1	45	21845
39+	-21846	1	46	21845
40	-21846	1	46	-21846
40+	-21846	0	40	21845
41	-21846	0	40	21845
41	-21846	0	41	21845
41	-21846	0	42	21845
41	-21846	0	43	21845
41	-21846	0	44	21845
41	-21846	0	45	21845
41	-21846	0	46	-21846
41	-21846	0	47	21845
41+	21845	1	46	-21846
42	21845	1	46	21845
42+	-21846	1	47	21845
43	-21846	1	47	-21846
43+	-21846	0	40	21845
44	-21846	0	40	21845
44	-21846	0	41	21845
44	-21846	0	42	21845
44	-21846	0	43	21845
44	-21846	0	44	21845
44	-21846	0	45	21845
44	-21846	0	46	21845
44	-21846	0	47	-21846
44+	21845	1	47	-21846
45	21845	1	47	21845
45+	21845	0	40	21845
46	21845	0	40	21845
46	21845	0	41	21845
46	21845	0	42	21845
46	21845	0	43	21845
46	21845	0	44	21845
46	21845	0	45	21845
46	21845	0	46	21845
46	21845	0	47	21845
46+	21845	0	5	0
47	21845	0	5	0
47	21845	0	13	1313
47	21845	0	21	0
47	21845	0	29	0
47	21845	0	37	0
47	21845	0	45	21845
47	21845	0	53	0
47	21845	0	61	0
47+	21845	1	5	0
48	21845	1	5	21845
48+	21845	1	13	1313
49	21845	1	13	21845
49+	21845	1	21	0
50	21845	1	21	21845
50+	21845	1	29	0
51	21845	1	29	21845
51+	21845	1	37	0
52	21845	1	37	21845
52+	21845	1	45	21845
53	21845	1	45	21845
53+	21845	1	53	0
54	21845	1	53	21845
54+	21845	1	61	0
55	21845	1	61	21845
55+	21845	0	5	21845
56	21845	0	5	21845
56	21845	0	13	21845
56	21845	0	21	21845
56	21845	0	29	21845
56	21845	0	37	21845
56	21845	0	45	21845
56	21845	0	53	21845
56	21845	0	61	21845
56+	-21846	1	5	21845
57	-21846	1	5	-21846
57+	-21846	0	5	-21846
58	-21846	0	5	-21846
58	-21846	0	13	21845
58	-21846	0	21	21845
58	-21846	0	29	21845
58	-21846	0	37	21845
58	-21846	0	45	21845
58	-21846	0	53	21845
58	-21846	0	61	21845
58+	21845	1	5	-21846
59	21845	1	5	21845
59+	-21846	1	13	21845
60	-21846	1	13	-21846
60+	-21846	0	5	21845
61	-21846	0	5	21845
61	-21846	0	13	-21846
61	-21846	0	21	21845
61	-21846	0	29	21845
61	-21846	0	37	21845
61	-21846	0	45	21845
61	-21846	0	53	21845
61	-21846	0	61	21845
61+	21845	1	13	-21846
62	21845	1	13	21845
62+	-21846	1	21	21845
63	-21846	1	21	-21846
63+	-21846	0	5	21845
64	-21846	0	5	21845
64	-21846	0	13	21845
64	-21846	0	21	-21846
64	-21846	0	29	21845
64	-21846	0	37	21845
64	-21846	0	45	21845
64	-21846	0	53	21845
64	-21846	0	61	21845
64+	21845	1	21	-21846
65	21845	1	21	21845
65+	-21846	1	29	21845
66	-21846	1	29	-21846
66+	-21846	0	5	21845
67	-21846	0	5	21845
67	-21846	0	13	21845
67	-21846	0	21	21845
67	-21846	0	29	-21846
67	-21846	0	37	21845
67	-21846	0	45	21845
67	-21846	0	53	21845
67	-21846	0	61	21845
67+	21845	1	29	-21846
68	21845	1	29	21845
68+	-21846	1	37	21845
69	-21846	1	37	-21846
69+	-21846	0	5	21845
70	-21846	0	5	21845
70	-21846	0	13	21845
70	-21846	0	21	21845
70	-21846	0	29	21845
70	-21846	0	37	-21846
70	-21846	0	45	21845
70	-21846	0	53	21845
70	-21846	0	61	21845
70+	21845	1	37	-21846
71	21845	1	37	21845
71+	-21846	1	45	21845
72	-21846	1	45	-21846
72+	-21846	0	5	21845
73	-21846	0	5	21845
73	-21846	0	13	21845
73	-21846	0	21	21845
73	-21846	0	29	21845
73	-21846	0	37	21845
73	-21846	0	45	-21846
73	-21846	0	53	21845
73	-21846	0	61	21845
73+	21845	1	45	-21846
74	21845	1	45	21845
74+	-21846	1	53	21845
75	-21846	1	53	-21846
75+	-21846	0	5	21845
76	-21846	0	5	21845
76	-21846	0	13	21845
76	-21846	0	21	21845
76	-21846	0	29	21845
76	-21846	0	37	21845
76	-21846	0	45	21845
76	-21846	0	53	-21846
76	-21846	0	61	21845
76+	21845	1	53	-21846
77	21845	1	53	21845
77+	-21846	1	61	21845
78	-21846	1	61	-21846
78+	-21846	0	5	21845
79	-21846	0	5	21845
79	-21846	0	13	21845
79	-21846	0	21	21845
79	-21846	0	29	21845
79	-21846	0	37	21845
79	-21846	0	45	21845
79	-21846	0	53	21845
79	-21846	0	61	-21846
79+	21845	1	61	-21846
80	21845	1	61	21845
80+	21845	0	5	21845
81	21845	0	5	21845
81	21845	0	13	21845
81	21845	0	21	21845
81	21845	0	29	21845
81	21845	0	37	21845
81	21845	0	45	21845
81	21845	0	53	21845
81	21845	0	61	21845

电路图

代码实现

CHIP RAM64 {
    IN in[16], load, address[6];
    OUT out[16];

    PARTS:
    DMux8Way(in = load, sel = address[3..5], a = a0, b = a1, c = a2,
    d = a3, e = a4, f = a5, g = a6, h = a7);
    RAM8(in = in, load = a0, address = address[0..2], out = out0);
    RAM8(in = in, load = a1, address = address[0..2], out = out1);
    RAM8(in = in, load = a2, address = address[0..2], out = out2);
    RAM8(in = in, load = a3, address = address[0..2], out = out3);
    RAM8(in = in, load = a4, address = address[0..2], out = out4);
    RAM8(in = in, load = a5, address = address[0..2], out = out5);
    RAM8(in = in, load = a6, address = address[0..2], out = out6);
    RAM8(in = in, load = a7, address = address[0..2], out = out7);
    Mux8Way16(a = out0, b = out1, c = out2, d = out3, e = out4,
    f = out5, g = out6, h = out7, sel = address[3..5], out = out);
}

运行结果

RAM512 512-register 存储器

真值表

time	in	load	address	out
0+	0	0	0	0
1	0	0	0	0
1+	0	1	0	0
2	0	1	0	0
2+	13099	0	0	0
3	13099	0	0	0
3+	13099	1	130	0
4	13099	1	130	13099
4+	13099	0	0	0
5	13099	0	0	0
5+	4729	0	472	0
6	4729	0	472	0
6+	4729	1	472	0
7	4729	1	472	4729
7+	4729	0	472	4729
8	4729	0	472	4729
8	4729	0	130	13099
8+	5119	0	130	13099
9	5119	0	130	13099
9+	5119	1	511	0
10	5119	1	511	5119
10+	5119	0	511	5119
11	5119	0	511	5119
11	5119	0	472	4729
11	5119	0	511	5119
11+	5119	0	168	0
12	5119	0	168	0
12	5119	0	169	0
12	5119	0	170	0
12	5119	0	171	0
12	5119	0	172	0
12	5119	0	173	0
12	5119	0	174	0
12	5119	0	175	0
12+	21845	1	168	0
13	21845	1	168	21845
13+	21845	1	169	0
14	21845	1	169	21845
14+	21845	1	170	0
15	21845	1	170	21845
15+	21845	1	171	0
16	21845	1	171	21845
16+	21845	1	172	0
17	21845	1	172	21845
17+	21845	1	173	0
18	21845	1	173	21845
18+	21845	1	174	0
19	21845	1	174	21845
19+	21845	1	175	0
20	21845	1	175	21845
20+	21845	0	168	21845
21	21845	0	168	21845
21	21845	0	169	21845
21	21845	0	170	21845
21	21845	0	171	21845
21	21845	0	172	21845
21	21845	0	173	21845
21	21845	0	174	21845
21	21845	0	175	21845
21+	-21846	1	168	21845
22	-21846	1	168	-21846
22+	-21846	0	168	-21846
23	-21846	0	168	-21846
23	-21846	0	169	21845
23	-21846	0	170	21845
23	-21846	0	171	21845
23	-21846	0	172	21845
23	-21846	0	173	21845
23	-21846	0	174	21845
23	-21846	0	175	21845
23+	21845	1	168	-21846
24	21845	1	168	21845
24+	-21846	1	169	21845
25	-21846	1	169	-21846
25+	-21846	0	168	21845
26	-21846	0	168	21845
26	-21846	0	169	-21846
26	-21846	0	170	21845
26	-21846	0	171	21845
26	-21846	0	172	21845
26	-21846	0	173	21845
26	-21846	0	174	21845
26	-21846	0	175	21845
26+	21845	1	169	-21846
27	21845	1	169	21845
27+	-21846	1	170	21845
28	-21846	1	170	-21846
28+	-21846	0	168	21845
29	-21846	0	168	21845
29	-21846	0	169	21845
29	-21846	0	170	-21846
29	-21846	0	171	21845
29	-21846	0	172	21845
29	-21846	0	173	21845
29	-21846	0	174	21845
29	-21846	0	175	21845
29+	21845	1	170	-21846
30	21845	1	170	21845
30+	-21846	1	171	21845
31	-21846	1	171	-21846
31+	-21846	0	168	21845
32	-21846	0	168	21845
32	-21846	0	169	21845
32	-21846	0	170	21845
32	-21846	0	171	-21846
32	-21846	0	172	21845
32	-21846	0	173	21845
32	-21846	0	174	21845
32	-21846	0	175	21845
32+	21845	1	171	-21846
33	21845	1	171	21845
33+	-21846	1	172	21845
34	-21846	1	172	-21846
34+	-21846	0	168	21845
35	-21846	0	168	21845
35	-21846	0	169	21845
35	-21846	0	170	21845
35	-21846	0	171	21845
35	-21846	0	172	-21846
35	-21846	0	173	21845
35	-21846	0	174	21845
35	-21846	0	175	21845
35+	21845	1	172	-21846
36	21845	1	172	21845
36+	-21846	1	173	21845
37	-21846	1	173	-21846
37+	-21846	0	168	21845
38	-21846	0	168	21845
38	-21846	0	169	21845
38	-21846	0	170	21845
38	-21846	0	171	21845
38	-21846	0	172	21845
38	-21846	0	173	-21846
38	-21846	0	174	21845
38	-21846	0	175	21845
38+	21845	1	173	-21846
39	21845	1	173	21845
39+	-21846	1	174	21845
40	-21846	1	174	-21846
40+	-21846	0	168	21845
41	-21846	0	168	21845
41	-21846	0	169	21845
41	-21846	0	170	21845
41	-21846	0	171	21845
41	-21846	0	172	21845
41	-21846	0	173	21845
41	-21846	0	174	-21846
41	-21846	0	175	21845
41+	21845	1	174	-21846
42	21845	1	174	21845
42+	-21846	1	175	21845
43	-21846	1	175	-21846
43+	-21846	0	168	21845
44	-21846	0	168	21845
44	-21846	0	169	21845
44	-21846	0	170	21845
44	-21846	0	171	21845
44	-21846	0	172	21845
44	-21846	0	173	21845
44	-21846	0	174	21845
44	-21846	0	175	-21846
44+	21845	1	175	-21846
45	21845	1	175	21845
45+	21845	0	168	21845
46	21845	0	168	21845
46	21845	0	169	21845
46	21845	0	170	21845
46	21845	0	171	21845
46	21845	0	172	21845
46	21845	0	173	21845
46	21845	0	174	21845
46	21845	0	175	21845
46+	21845	0	42	0
47	21845	0	42	0
47	21845	0	106	0
47	21845	0	170	21845
47	21845	0	234	0
47	21845	0	298	0
47	21845	0	362	0
47	21845	0	426	0
47	21845	0	490	0
47+	21845	1	42	0
48	21845	1	42	21845
48+	21845	1	106	0
49	21845	1	106	21845
49+	21845	1	170	21845
50	21845	1	170	21845
50+	21845	1	234	0
51	21845	1	234	21845
51+	21845	1	298	0
52	21845	1	298	21845
52+	21845	1	362	0
53	21845	1	362	21845
53+	21845	1	426	0
54	21845	1	426	21845
54+	21845	1	490	0
55	21845	1	490	21845
55+	21845	0	42	21845
56	21845	0	42	21845
56	21845	0	106	21845
56	21845	0	170	21845
56	21845	0	234	21845
56	21845	0	298	21845
56	21845	0	362	21845
56	21845	0	426	21845
56	21845	0	490	21845
56+	-21846	1	42	21845
57	-21846	1	42	-21846
57+	-21846	0	42	-21846
58	-21846	0	42	-21846
58	-21846	0	106	21845
58	-21846	0	170	21845
58	-21846	0	234	21845
58	-21846	0	298	21845
58	-21846	0	362	21845
58	-21846	0	426	21845
58	-21846	0	490	21845
58+	21845	1	42	-21846
59	21845	1	42	21845
59+	-21846	1	106	21845
60	-21846	1	106	-21846
60+	-21846	0	42	21845
61	-21846	0	42	21845
61	-21846	0	106	-21846
61	-21846	0	170	21845
61	-21846	0	234	21845
61	-21846	0	298	21845
61	-21846	0	362	21845
61	-21846	0	426	21845
61	-21846	0	490	21845
61+	21845	1	106	-21846
62	21845	1	106	21845
62+	-21846	1	170	21845
63	-21846	1	170	-21846
63+	-21846	0	42	21845
64	-21846	0	42	21845
64	-21846	0	106	21845
64	-21846	0	170	-21846
64	-21846	0	234	21845
64	-21846	0	298	21845
64	-21846	0	362	21845
64	-21846	0	426	21845
64	-21846	0	490	21845
64+	21845	1	170	-21846
65	21845	1	170	21845
65+	-21846	1	234	21845
66	-21846	1	234	-21846
66+	-21846	0	42	21845
67	-21846	0	42	21845
67	-21846	0	106	21845
67	-21846	0	170	21845
67	-21846	0	234	-21846
67	-21846	0	298	21845
67	-21846	0	362	21845
67	-21846	0	426	21845
67	-21846	0	490	21845
67+	21845	1	234	-21846
68	21845	1	234	21845
68+	-21846	1	298	21845
69	-21846	1	298	-21846
69+	-21846	0	42	21845
70	-21846	0	42	21845
70	-21846	0	106	21845
70	-21846	0	170	21845
70	-21846	0	234	21845
70	-21846	0	298	-21846
70	-21846	0	362	21845
70	-21846	0	426	21845
70	-21846	0	490	21845
70+	21845	1	298	-21846
71	21845	1	298	21845
71+	-21846	1	362	21845
72	-21846	1	362	-21846
72+	-21846	0	42	21845
73	-21846	0	42	21845
73	-21846	0	106	21845
73	-21846	0	170	21845
73	-21846	0	234	21845
73	-21846	0	298	21845
73	-21846	0	362	-21846
73	-21846	0	426	21845
73	-21846	0	490	21845
73+	21845	1	362	-21846
74	21845	1	362	21845
74+	-21846	1	426	21845
75	-21846	1	426	-21846
75+	-21846	0	42	21845
76	-21846	0	42	21845
76	-21846	0	106	21845
76	-21846	0	170	21845
76	-21846	0	234	21845
76	-21846	0	298	21845
76	-21846	0	362	21845
76	-21846	0	426	-21846
76	-21846	0	490	21845
76+	21845	1	426	-21846
77	21845	1	426	21845
77+	-21846	1	490	21845
78	-21846	1	490	-21846
78+	-21846	0	42	21845
79	-21846	0	42	21845
79	-21846	0	106	21845
79	-21846	0	170	21845
79	-21846	0	234	21845
79	-21846	0	298	21845
79	-21846	0	362	21845
79	-21846	0	426	21845
79	-21846	0	490	-21846
79+	21845	1	490	-21846
80	21845	1	490	21845
80+	21845	0	42	21845
81	21845	0	42	21845
81	21845	0	106	21845
81	21845	0	170	21845
81	21845	0	234	21845
81	21845	0	298	21845
81	21845	0	362	21845
81	21845	0	426	21845
81	21845	0	490	21845

电路图

代码实现

CHIP RAM512 {
    IN in[16], load, address[9];
    OUT out[16];

    PARTS:
    DMux8Way(in = load, sel = address[6..8], a = a0, b = a1, c = a2,
    d = a3, e = a4, f = a5, g = a6, h = a7);
    RAM64(in = in, load = a0, address = address[0..5], out = out0);
    RAM64(in = in, load = a1, address = address[0..5], out = out1);
    RAM64(in = in, load = a2, address = address[0..5], out = out2);
    RAM64(in = in, load = a3, address = address[0..5], out = out3);
    RAM64(in = in, load = a4, address = address[0..5], out = out4);
    RAM64(in = in, load = a5, address = address[0..5], out = out5);
    RAM64(in = in, load = a6, address = address[0..5], out = out6);
    RAM64(in = in, load = a7, address = address[0..5], out = out7);
    Mux8Way16(a = out0, b = out1, c = out2, d = out3, e = out4,
    f = out5, g = out6, h = out7, sel = address[6..8], out = out);
}

运行结果

RAM4K 4096-register 存储器

真值表

time	in	load	address	out
0+	0	0	0	0
1	0	0	0	0
1+	0	1	0	0
2	0	1	0	0
2+	1111	0	0	0
3	1111	0	0	0
3+	1111	1	1111	0
4	1111	1	1111	1111
4+	1111	0	0	0
5	1111	0	0	0
5+	3513	0	3513	0
6	3513	0	3513	0
6+	3513	1	3513	0
7	3513	1	3513	3513
7+	3513	0	3513	3513
8	3513	0	3513	3513
8	3513	0	1111	1111
8+	4095	0	1111	1111
9	4095	0	1111	1111
9+	4095	1	4095	0
10	4095	1	4095	4095
10+	4095	0	4095	4095
11	4095	0	4095	4095
11	4095	0	3513	3513
11	4095	0	4095	4095
11+	4095	0	2728	0
12	4095	0	2728	0
12	4095	0	2729	0
12	4095	0	2730	0
12	4095	0	2731	0
12	4095	0	2732	0
12	4095	0	2733	0
12	4095	0	2734	0
12	4095	0	2735	0
12+	21845	1	2728	0
13	21845	1	2728	21845
13+	21845	1	2729	0
14	21845	1	2729	21845
14+	21845	1	2730	0
15	21845	1	2730	21845
15+	21845	1	2731	0
16	21845	1	2731	21845
16+	21845	1	2732	0
17	21845	1	2732	21845
17+	21845	1	2733	0
18	21845	1	2733	21845
18+	21845	1	2734	0
19	21845	1	2734	21845
19+	21845	1	2735	0
20	21845	1	2735	21845
20+	21845	0	2728	21845
21	21845	0	2728	21845
21	21845	0	2729	21845
21	21845	0	2730	21845
21	21845	0	2731	21845
21	21845	0	2732	21845
21	21845	0	2733	21845
21	21845	0	2734	21845
21	21845	0	2735	21845
21+	-21846	1	2728	21845
22	-21846	1	2728	-21846
22+	-21846	0	2728	-21846
23	-21846	0	2728	-21846
23	-21846	0	2729	21845
23	-21846	0	2730	21845
23	-21846	0	2731	21845
23	-21846	0	2732	21845
23	-21846	0	2733	21845
23	-21846	0	2734	21845
23	-21846	0	2735	21845
23+	21845	1	2728	-21846
24	21845	1	2728	21845
24+	-21846	1	2729	21845
25	-21846	1	2729	-21846
25+	-21846	0	2728	21845
26	-21846	0	2728	21845
26	-21846	0	2729	-21846
26	-21846	0	2730	21845
26	-21846	0	2731	21845
26	-21846	0	2732	21845
26	-21846	0	2733	21845
26	-21846	0	2734	21845
26	-21846	0	2735	21845
26+	21845	1	2729	-21846
27	21845	1	2729	21845
27+	-21846	1	2730	21845
28	-21846	1	2730	-21846
28+	-21846	0	2728	21845
29	-21846	0	2728	21845
29	-21846	0	2729	21845
29	-21846	0	2730	-21846
29	-21846	0	2731	21845
29	-21846	0	2732	21845
29	-21846	0	2733	21845
29	-21846	0	2734	21845
29	-21846	0	2735	21845
29+	21845	1	2730	-21846
30	21845	1	2730	21845
30+	-21846	1	2731	21845
31	-21846	1	2731	-21846
31+	-21846	0	2728	21845
32	-21846	0	2728	21845
32	-21846	0	2729	21845
32	-21846	0	2730	21845
32	-21846	0	2731	-21846
32	-21846	0	2732	21845
32	-21846	0	2733	21845
32	-21846	0	2734	21845
32	-21846	0	2735	21845
32+	21845	1	2731	-21846
33	21845	1	2731	21845
33+	-21846	1	2732	21845
34	-21846	1	2732	-21846
34+	-21846	0	2728	21845
35	-21846	0	2728	21845
35	-21846	0	2729	21845
35	-21846	0	2730	21845
35	-21846	0	2731	21845
35	-21846	0	2732	-21846
35	-21846	0	2733	21845
35	-21846	0	2734	21845
35	-21846	0	2735	21845
35+	21845	1	2732	-21846
36	21845	1	2732	21845
36+	-21846	1	2733	21845
37	-21846	1	2733	-21846
37+	-21846	0	2728	21845
38	-21846	0	2728	21845
38	-21846	0	2729	21845
38	-21846	0	2730	21845
38	-21846	0	2731	21845
38	-21846	0	2732	21845
38	-21846	0	2733	-21846
38	-21846	0	2734	21845
38	-21846	0	2735	21845
38+	21845	1	2733	-21846
39	21845	1	2733	21845
39+	-21846	1	2734	21845
40	-21846	1	2734	-21846
40+	-21846	0	2728	21845
41	-21846	0	2728	21845
41	-21846	0	2729	21845
41	-21846	0	2730	21845
41	-21846	0	2731	21845
41	-21846	0	2732	21845
41	-21846	0	2733	21845
41	-21846	0	2734	-21846
41	-21846	0	2735	21845
41+	21845	1	2734	-21846
42	21845	1	2734	21845
42+	-21846	1	2735	21845
43	-21846	1	2735	-21846
43+	-21846	0	2728	21845
44	-21846	0	2728	21845
44	-21846	0	2729	21845
44	-21846	0	2730	21845
44	-21846	0	2731	21845
44	-21846	0	2732	21845
44	-21846	0	2733	21845
44	-21846	0	2734	21845
44	-21846	0	2735	-21846
44+	21845	1	2735	-21846
45	21845	1	2735	21845
45+	21845	0	2728	21845
46	21845	0	2728	21845
46	21845	0	2729	21845
46	21845	0	2730	21845
46	21845	0	2731	21845
46	21845	0	2732	21845
46	21845	0	2733	21845
46	21845	0	2734	21845
46	21845	0	2735	21845
46+	21845	0	341	0
47	21845	0	341	0
47	21845	0	853	0
47	21845	0	1365	0
47	21845	0	1877	0
47	21845	0	2389	0
47	21845	0	2901	0
47	21845	0	3413	0
47	21845	0	3925	0
47+	21845	1	341	0
48	21845	1	341	21845
48+	21845	1	853	0
49	21845	1	853	21845
49+	21845	1	1365	0
50	21845	1	1365	21845
50+	21845	1	1877	0
51	21845	1	1877	21845
51+	21845	1	2389	0
52	21845	1	2389	21845
52+	21845	1	2901	0
53	21845	1	2901	21845
53+	21845	1	3413	0
54	21845	1	3413	21845
54+	21845	1	3925	0
55	21845	1	3925	21845
55+	21845	0	341	21845
56	21845	0	341	21845
56	21845	0	853	21845
56	21845	0	1365	21845
56	21845	0	1877	21845
56	21845	0	2389	21845
56	21845	0	2901	21845
56	21845	0	3413	21845
56	21845	0	3925	21845
56+	-21846	1	341	21845
57	-21846	1	341	-21846
57+	-21846	0	341	-21846
58	-21846	0	341	-21846
58	-21846	0	853	21845
58	-21846	0	1365	21845
58	-21846	0	1877	21845
58	-21846	0	2389	21845
58	-21846	0	2901	21845
58	-21846	0	3413	21845
58	-21846	0	3925	21845
58+	21845	1	341	-21846
59	21845	1	341	21845
59+	-21846	1	853	21845
60	-21846	1	853	-21846
60+	-21846	0	341	21845
61	-21846	0	341	21845
61	-21846	0	853	-21846
61	-21846	0	1365	21845
61	-21846	0	1877	21845
61	-21846	0	2389	21845
61	-21846	0	2901	21845
61	-21846	0	3413	21845
61	-21846	0	3925	21845
61+	21845	1	853	-21846
62	21845	1	853	21845
62+	-21846	1	1365	21845
63	-21846	1	1365	-21846
63+	-21846	0	341	21845
64	-21846	0	341	21845
64	-21846	0	853	21845
64	-21846	0	1365	-21846
64	-21846	0	1877	21845
64	-21846	0	2389	21845
64	-21846	0	2901	21845
64	-21846	0	3413	21845
64	-21846	0	3925	21845
64+	21845	1	1365	-21846
65	21845	1	1365	21845
65+	-21846	1	1877	21845
66	-21846	1	1877	-21846
66+	-21846	0	341	21845
67	-21846	0	341	21845
67	-21846	0	853	21845
67	-21846	0	1365	21845
67	-21846	0	1877	-21846
67	-21846	0	2389	21845
67	-21846	0	2901	21845
67	-21846	0	3413	21845
67	-21846	0	3925	21845
67+	21845	1	1877	-21846
68	21845	1	1877	21845
68+	-21846	1	2389	21845
69	-21846	1	2389	-21846
69+	-21846	0	341	21845
70	-21846	0	341	21845
70	-21846	0	853	21845
70	-21846	0	1365	21845
70	-21846	0	1877	21845
70	-21846	0	2389	-21846
70	-21846	0	2901	21845
70	-21846	0	3413	21845
70	-21846	0	3925	21845
70+	21845	1	2389	-21846
71	21845	1	2389	21845
71+	-21846	1	2901	21845
72	-21846	1	2901	-21846
72+	-21846	0	341	21845
73	-21846	0	341	21845
73	-21846	0	853	21845
73	-21846	0	1365	21845
73	-21846	0	1877	21845
73	-21846	0	2389	21845
73	-21846	0	2901	-21846
73	-21846	0	3413	21845
73	-21846	0	3925	21845
73+	21845	1	2901	-21846
74	21845	1	2901	21845
74+	-21846	1	3413	21845
75	-21846	1	3413	-21846
75+	-21846	0	341	21845
76	-21846	0	341	21845
76	-21846	0	853	21845
76	-21846	0	1365	21845
76	-21846	0	1877	21845
76	-21846	0	2389	21845
76	-21846	0	2901	21845
76	-21846	0	3413	-21846
76	-21846	0	3925	21845
76+	21845	1	3413	-21846
77	21845	1	3413	21845
77+	-21846	1	3925	21845
78	-21846	1	3925	-21846
78+	-21846	0	341	21845
79	-21846	0	341	21845
79	-21846	0	853	21845
79	-21846	0	1365	21845
79	-21846	0	1877	21845
79	-21846	0	2389	21845
79	-21846	0	2901	21845
79	-21846	0	3413	21845
79	-21846	0	3925	-21846
79+	21845	1	3925	-21846
80	21845	1	3925	21845
80+	21845	0	341	21845
81	21845	0	341	21845
81	21845	0	853	21845
81	21845	0	1365	21845
81	21845	0	1877	21845
81	21845	0	2389	21845
81	21845	0	2901	21845
81	21845	0	3413	21845
81	21845	0	3925	21845

电路图

代码实现

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:
    DMux8Way(in = load, sel = address[9..11], a = a0, b = a1, c = a2,
    d = a3, e = a4, f = a5, g = a6, h = a7);
    RAM512(in = in, load = a0, address = address[0..8], out = out0);
    RAM512(in = in, load = a1, address = address[0..8], out = out1);
    RAM512(in = in, load = a2, address = address[0..8], out = out2);
    RAM512(in = in, load = a3, address = address[0..8], out = out3);
    RAM512(in = in, load = a4, address = address[0..8], out = out4);
    RAM512(in = in, load = a5, address = address[0..8], out = out5);
    RAM512(in = in, load = a6, address = address[0..8], out = out6);
    RAM512(in = in, load = a7, address = address[0..8], out = out7);
    Mux8Way16(a = out0, b = out1, c = out2, d = out3, e = out4,
    f = out5, g = out6, h = out7, sel = address[9..11], out = out);
}

运行结果

RAM16K 16384-register 存储器

真值表

time	in	load	address	out
0+	0	0	0	0
1	0	0	0	0
1+	0	1	0	0
2	0	1	0	0
2+	4321	0	0	0
3	4321	0	0	0
3+	4321	1	4321	0
4	4321	1	4321	4321
4+	4321	0	0	0
5	4321	0	0	0
5+	12345	0	12345	0
6	12345	0	12345	0
6+	12345	1	12345	0
7	12345	1	12345	12345
7+	12345	0	12345	12345
8	12345	0	12345	12345
8	12345	0	4321	4321
8+	16383	0	4321	4321
9	16383	0	4321	4321
9+	16383	1	16383	0
10	16383	1	16383	16383
10+	16383	0	16383	16383
11	16383	0	16383	16383
11	16383	0	12345	12345
11	16383	0	16383	16383
11+	16383	0	10920	0
12	16383	0	10920	0
12	16383	0	10921	0
12	16383	0	10922	0
12	16383	0	10923	0
12	16383	0	10924	0
12	16383	0	10925	0
12	16383	0	10926	0
12	16383	0	10927	0
12+	21845	1	10920	0
13	21845	1	10920	21845
13+	21845	1	10921	0
14	21845	1	10921	21845
14+	21845	1	10922	0
15	21845	1	10922	21845
15+	21845	1	10923	0
16	21845	1	10923	21845
16+	21845	1	10924	0
17	21845	1	10924	21845
17+	21845	1	10925	0
18	21845	1	10925	21845
18+	21845	1	10926	0
19	21845	1	10926	21845
19+	21845	1	10927	0
20	21845	1	10927	21845
20+	21845	0	10920	21845
21	21845	0	10920	21845
21	21845	0	10921	21845
21	21845	0	10922	21845
21	21845	0	10923	21845
21	21845	0	10924	21845
21	21845	0	10925	21845
21	21845	0	10926	21845
21	21845	0	10927	21845
21+	-21846	1	10920	21845
22	-21846	1	10920	-21846
22+	-21846	0	10920	-21846
23	-21846	0	10920	-21846
23	-21846	0	10921	21845
23	-21846	0	10922	21845
23	-21846	0	10923	21845
23	-21846	0	10924	21845
23	-21846	0	10925	21845
23	-21846	0	10926	21845
23	-21846	0	10927	21845
23+	21845	1	10920	-21846
24	21845	1	10920	21845
24+	-21846	1	10921	21845
25	-21846	1	10921	-21846
25+	-21846	0	10920	21845
26	-21846	0	10920	21845
26	-21846	0	10921	-21846
26	-21846	0	10922	21845
26	-21846	0	10923	21845
26	-21846	0	10924	21845
26	-21846	0	10925	21845
26	-21846	0	10926	21845
26	-21846	0	10927	21845
26+	21845	1	10921	-21846
27	21845	1	10921	21845
27+	-21846	1	10922	21845
28	-21846	1	10922	-21846
28+	-21846	0	10920	21845
29	-21846	0	10920	21845
29	-21846	0	10921	21845
29	-21846	0	10922	-21846
29	-21846	0	10923	21845
29	-21846	0	10924	21845
29	-21846	0	10925	21845
29	-21846	0	10926	21845
29	-21846	0	10927	21845
29+	21845	1	10922	-21846
30	21845	1	10922	21845
30+	-21846	1	10923	21845
31	-21846	1	10923	-21846
31+	-21846	0	10920	21845
32	-21846	0	10920	21845
32	-21846	0	10921	21845
32	-21846	0	10922	21845
32	-21846	0	10923	-21846
32	-21846	0	10924	21845
32	-21846	0	10925	21845
32	-21846	0	10926	21845
32	-21846	0	10927	21845
32+	21845	1	10923	-21846
33	21845	1	10923	21845
33+	-21846	1	10924	21845
34	-21846	1	10924	-21846
34+	-21846	0	10920	21845
35	-21846	0	10920	21845
35	-21846	0	10921	21845
35	-21846	0	10922	21845
35	-21846	0	10923	21845
35	-21846	0	10924	-21846
35	-21846	0	10925	21845
35	-21846	0	10926	21845
35	-21846	0	10927	21845
35+	21845	1	10924	-21846
36	21845	1	10924	21845
36+	-21846	1	10925	21845
37	-21846	1	10925	-21846
37+	-21846	0	10920	21845
38	-21846	0	10920	21845
38	-21846	0	10921	21845
38	-21846	0	10922	21845
38	-21846	0	10923	21845
38	-21846	0	10924	21845
38	-21846	0	10925	-21846
38	-21846	0	10926	21845
38	-21846	0	10927	21845
38+	21845	1	10925	-21846
39	21845	1	10925	21845
39+	-21846	1	10926	21845
40	-21846	1	10926	-21846
40+	-21846	0	10920	21845
41	-21846	0	10920	21845
41	-21846	0	10921	21845
41	-21846	0	10922	21845
41	-21846	0	10923	21845
41	-21846	0	10924	21845
41	-21846	0	10925	21845
41	-21846	0	10926	-21846
41	-21846	0	10927	21845
41+	21845	1	10926	-21846
42	21845	1	10926	21845
42+	-21846	1	10927	21845
43	-21846	1	10927	-21846
43+	-21846	0	10920	21845
44	-21846	0	10920	21845
44	-21846	0	10921	21845
44	-21846	0	10922	21845
44	-21846	0	10923	21845
44	-21846	0	10924	21845
44	-21846	0	10925	21845
44	-21846	0	10926	21845
44	-21846	0	10927	-21846
44+	21845	1	10927	-21846
45	21845	1	10927	21845
45+	21845	0	10920	21845
46	21845	0	10920	21845
46	21845	0	10921	21845
46	21845	0	10922	21845
46	21845	0	10923	21845
46	21845	0	10924	21845
46	21845	0	10925	21845
46	21845	0	10926	21845
46	21845	0	10927	21845
46+	21845	0	1365	0
47	21845	0	1365	0
47	21845	0	3413	0
47	21845	0	5461	0
47	21845	0	7509	0
47	21845	0	9557	0
47	21845	0	11605	0
47	21845	0	13653	0
47	21845	0	15701	0
47+	21845	1	1365	0
48	21845	1	1365	21845
48+	21845	1	3413	0
49	21845	1	3413	21845
49+	21845	1	5461	0
50	21845	1	5461	21845
50+	21845	1	7509	0
51	21845	1	7509	21845
51+	21845	1	9557	0
52	21845	1	9557	21845
52+	21845	1	11605	0
53	21845	1	11605	21845
53+	21845	1	13653	0
54	21845	1	13653	21845
54+	21845	1	15701	0
55	21845	1	15701	21845
55+	21845	0	1365	21845
56	21845	0	1365	21845
56	21845	0	3413	21845
56	21845	0	5461	21845
56	21845	0	7509	21845
56	21845	0	9557	21845
56	21845	0	11605	21845
56	21845	0	13653	21845
56	21845	0	15701	21845
56+	-21846	1	1365	21845
57	-21846	1	1365	-21846
57+	-21846	0	1365	-21846
58	-21846	0	1365	-21846
58	-21846	0	3413	21845
58	-21846	0	5461	21845
58	-21846	0	7509	21845
58	-21846	0	9557	21845
58	-21846	0	11605	21845
58	-21846	0	13653	21845
58	-21846	0	15701	21845
58+	21845	1	1365	-21846
59	21845	1	1365	21845
59+	-21846	1	3413	21845
60	-21846	1	3413	-21846
60+	-21846	0	1365	21845
61	-21846	0	1365	21845
61	-21846	0	3413	-21846
61	-21846	0	5461	21845
61	-21846	0	7509	21845
61	-21846	0	9557	21845
61	-21846	0	11605	21845
61	-21846	0	13653	21845
61	-21846	0	15701	21845
61+	21845	1	3413	-21846
62	21845	1	3413	21845
62+	-21846	1	5461	21845
63	-21846	1	5461	-21846
63+	-21846	0	1365	21845
64	-21846	0	1365	21845
64	-21846	0	3413	21845
64	-21846	0	5461	-21846
64	-21846	0	7509	21845
64	-21846	0	9557	21845
64	-21846	0	11605	21845
64	-21846	0	13653	21845
64	-21846	0	15701	21845
64+	21845	1	5461	-21846
65	21845	1	5461	21845
65+	-21846	1	7509	21845
66	-21846	1	7509	-21846
66+	-21846	0	1365	21845
67	-21846	0	1365	21845
67	-21846	0	3413	21845
67	-21846	0	5461	21845
67	-21846	0	7509	-21846
67	-21846	0	9557	21845
67	-21846	0	11605	21845
67	-21846	0	13653	21845
67	-21846	0	15701	21845
67+	21845	1	7509	-21846
68	21845	1	7509	21845
68+	-21846	1	9557	21845
69	-21846	1	9557	-21846
69+	-21846	0	1365	21845
70	-21846	0	1365	21845
70	-21846	0	3413	21845
70	-21846	0	5461	21845
70	-21846	0	7509	21845
70	-21846	0	9557	-21846
70	-21846	0	11605	21845
70	-21846	0	13653	21845
70	-21846	0	15701	21845
70+	21845	1	9557	-21846
71	21845	1	9557	21845
71+	-21846	1	11605	21845
72	-21846	1	11605	-21846
72+	-21846	0	1365	21845
73	-21846	0	1365	21845
73	-21846	0	3413	21845
73	-21846	0	5461	21845
73	-21846	0	7509	21845
73	-21846	0	9557	21845
73	-21846	0	11605	-21846
73	-21846	0	13653	21845
73	-21846	0	15701	21845
73+	21845	1	11605	-21846
74	21845	1	11605	21845
74+	-21846	1	13653	21845
75	-21846	1	13653	-21846
75+	-21846	0	1365	21845
76	-21846	0	1365	21845
76	-21846	0	3413	21845
76	-21846	0	5461	21845
76	-21846	0	7509	21845
76	-21846	0	9557	21845
76	-21846	0	11605	21845
76	-21846	0	13653	-21846
76	-21846	0	15701	21845
76+	21845	1	13653	-21846
77	21845	1	13653	21845
77+	-21846	1	15701	21845
78	-21846	1	15701	-21846
78+	-21846	0	1365	21845
79	-21846	0	1365	21845
79	-21846	0	3413	21845
79	-21846	0	5461	21845
79	-21846	0	7509	21845
79	-21846	0	9557	21845
79	-21846	0	11605	21845
79	-21846	0	13653	21845
79	-21846	0	15701	-21846
79+	21845	1	15701	-21846
80	21845	1	15701	21845
80+	21845	0	1365	21845
81	21845	0	1365	21845
81	21845	0	3413	21845
81	21845	0	5461	21845
81	21845	0	7509	21845
81	21845	0	9557	21845
81	21845	0	11605	21845
81	21845	0	13653	21845
81	21845	0	15701	21845

电路图

代码实现

CHIP RAM16K {
    IN in[16], load, address[14];
    OUT out[16];

    PARTS:
    DMux4Way(in = load, sel = address[12..13], a = a0, b = a1, c = a2, d = a3);
    RAM4K(in = in, load = a0, address = address[0..11], out = out0);
    RAM4K(in = in, load = a1, address = address[0..11], out = out1);
    RAM4K(in = in, load = a2, address = address[0..11], out = out2);
    RAM4K(in = in, load = a3, address = address[0..11], out = out3);
    Mux4Way16(a = out0, b = out1, c = out2, d = out3, sel = address[12..13], out = out);
}

运行结果

PC 16位程序计数器

虽然计数器(counter) 是独立的抽象, 但是可以通过它的一些应用来描述.比如, 考虑一个指令地址计数器, 它的内容是计算机下一时钟周期要读取和执行的指令地址.在大多数情况下, 计数器在每个时钟周期内做简单的"加1"操作, 因此计算机能够获取程序的下一条指令.在其他情况下, 比如要"跳跃去执行编号为n的指令"时, 我们希望能够将计数器设为n,然后它继续进行默认的计数行为, n+1/n+2, 等等.甚至, 将计数器
清零.在任何时候可通过将计数器置0来让程序重新执行.简单地说, 我们需要一个可重载的/可重置的计数器.
如此一来, 我们的计数器芯片接口就与寄存器的接口十分相似, 只是计数器芯片有两个附加的控制位reset 和inc. 当inc=1 时, 计数器在每个时钟周期自加, 输出值out(t)=out(t-1)+1.如果想要将计数器重置为0,就将reset位置为1;如果想要将其初始化为某个计数值d,就将d置于in输入管脚然后将load 位置1.

真值表

time	in	reset	load	inc	out
0+	0	0	0	0	0
1	0	0	0	0	0
1+	0	0	0	1	0
2	0	0	0	1	1
2+	-32123	0	0	1	1
3	-32123	0	0	1	2
3+	-32123	0	1	1	2
4	-32123	0	1	1	-32123
4+	-32123	0	0	1	-32123
5	-32123	0	0	1	-32122
5+	-32123	0	0	1	-32122
6	-32123	0	0	1	-32121
6+	12345	0	1	0	-32121
7	12345	0	1	0	12345
7+	12345	1	1	0	12345
8	12345	1	1	0	0
8+	12345	0	1	1	0
9	12345	0	1	1	12345
9+	12345	1	1	1	12345
10	12345	1	1	1	0
10+	12345	0	0	1	0
11	12345	0	0	1	1
11+	12345	1	0	1	1
12	12345	1	0	1	0
12+	0	0	1	1	0
13	0	0	1	1	0
13+	0	0	0	1	0
14	0	0	0	1	1
14+	22222	1	0	0	1
15	22222	1	0	0	0

电路图

代码实现

CHIP PC {
    IN in[16], load, inc, reset;
    OUT out[16];

    PARTS:
    Inc16(in=out4, out=incO);

    Mux16(a=out4, b=incO, sel=inc, out=out1);

    Mux16(a=out1, b=in, sel=load, out=out2);

    Mux16(a=out2, b[0]=false, sel=reset, out=out3);

    Register(in=out3, load=true, out=out4, out=out);
}

运行结果

流水线技术

什么是流水线

是指在程序执行时多条指令重叠进行操作的一种准并行处理实现技术.流水线是Intel首次在486芯片中开始使用的.在CPU中由5-6个不同功能的电路单元组成一条指令处理流水线, 然后将一条指令分成5-6步后再由这些电路单元分别执行, 这样就能实.现在一个CPU时钟周期完成一条指令, 因此提高CPU的运算速度.

流水线的实现

餐馆流水线的喇叭是时钟(clock)
计算机中用寄存器(register)隔离每个流水线环节.
流水线中的各个处理部件可并行工作, 从而可使整个程序的执行时间缩短
流水线并不会缩短单条指令的执行时间(甚至会增加时间) ,而是提高了指令的吞吐率
吞吐率有个公式:指令条数除以流水线时间

CHIP Mul {
  IN a[4], b[4];
  OUT s[8];

 PARTS:
 And(a=a[0], b=b[0], out=s[0]);

 And(a=a[1], b=b[0], out=a1b0);
 And(a=a[0], b=b[1], out=a0b1);
 HalfAdder(a=a1b0, b=a0b1, sum=s[1], carry=HCS1);

 And(a=a[2], b=b[0], out=a2b0);
 And(a=a[1], b=b[1], out=a1b1);
 HalfAdder(a=a2b0, b=a1b1, sum=HSS2, carry=HCS2);
 And(a=a[0], b=b[2], out=a0b2);
 FullAdder(a=HSS2, b=a0b2, c=HCS1, sum=s[2], carry=FHCS2);

 And(a=a[3], b=b[0], out=a3b0);
 And(a=a[2], b=b[1], out=a2b1);
 HalfAdder(a=a3b0, b=a2b1, sum=HSS3, carry=HCS3);
 And(a=a[1], b=b[2], out=a1b2);
 FullAdder(a=HSS3, b=a1b2, c=HCS2, sum=HFSS3, carry=HFCS3);
 And(a=a[0], b=b[3], out=a0b3);
 FullAdder(a=HFSS3, b=a0b3, c=FHCS2, sum=s[3], carry=HFFCS3);

 And(a=a[3], b=b[1], out=a3b1);
 And(a=a[2], b=b[2], out=a2b2);
 FullAdder(a=a3b1, b=a2b2, c=HCS3, sum=FSS4, carry=FCS4);
 And(a=a[1], b=b[3], out=a1b3);
 FullAdder(a=FSS4, b=a1b3, c=HFCS3, sum=FFSS4, carry=FFCS4);
 HalfAdder(a=FFSS4, b=HFFCS3, sum=s[4], carry=FFHCS4);

 And(a=a[3], b=b[2], out=a3b2);
 And(a=a[2], b=b[3], out=a2b3);
 FullAdder(a=a3b2, b=a2b3, c=FCS4, sum=FSS5, carry=FCS5);
 HalfAdder(a=FSS5, b=FFCS4, sum=FHSS5, carry=FHCS5);
 HalfAdder(a=FHSS5, b=FFHCS4, sum=s[5], carry=FHHCS5);

 And(a=a[3], b=b[3], out=a3b3);
 HalfAdder(a=a3b3, b=FCS5, sum=HSS6, carry=HCS6);
 FullAdder(a=HSS6, b=FHCS5, c=FHHCS5, sum=s[6], carry=HFCS6);

 HalfAdder(a=HCS6, b=HFCS6, sum=s[7], carry=carry);
}

CHIP PMul {
 IN a[4], b[4];
 OUT s[8];

 PARTS:
 And(a=a[0], b=b[0], out=sout0);
 DFF(in=sout0, out=s[0]);

 And(a=a[1], b=b[0], out=a1b0);
 And(a=a[0], b=b[1], out=a0b1);
 HalfAdder(a=a1b0, b=a0b1, sum=sout1, carry=HCS1);
 DFF(in=sout1, out=s[1]);

 And(a=a[2], b=b[0], out=a2b0);
 And(a=a[1], b=b[1], out=a1b1);
 HalfAdder(a=a2b0, b=a1b1, sum=HSS2, carry=HCS2);
 And(a=a[0], b=b[2], out=a0b2);
 FullAdder(a=HSS2, b=a0b2, c=HCS1, sum=sout2, carry=FHCS2);
 DFF(in=sout2, out=s[2]);

 And(a=a[3], b=b[0], out=a3b0);
 And(a=a[2], b=b[1], out=a2b1);
 HalfAdder(a=a3b0, b=a2b1, sum=HSS3, carry=HCS3);
 And(a=a[1], b=b[2], out=a1b2);
 FullAdder(a=HSS3, b=a1b2, c=HCS2, sum=HFSS3, carry=HFCS3);
 And(a=a[0], b=b[3], out=a0b3);
 FullAdder(a=HFSS3, b=a0b3, c=FHCS2, sum=sout3, carry=HFFCS3);
 DFF(in=sout3, out=s[3]);

 And(a=a[3], b=b[1], out=a3b1);
 And(a=a[2], b=b[2], out=a2b2);
 FullAdder(a=a3b1, b=a2b2, c=HCS3, sum=FSS4, carry=FCS4);
 And(a=a[1], b=b[3], out=a1b3);
 FullAdder(a=FSS4, b=a1b3, c=HFCS3, sum=FFSS4, carry=FFCS4);
 DFF(in=HFFCS3, out=sout4);
 DFF(in=FFSS4, out=sout5);
 HalfAdder(a=sout5, b=sout4, sum=s[4], carry=FFHCS4);

 And(a=a[3], b=b[2], out=a3b2);
 And(a=a[2], b=b[3], out=a2b3);
 FullAdder(a=a3b2, b=a2b3, c=FCS4, sum=FSS5, carry=FCS5);
 DFF(in=FFCS4, out=sout6);
 DFF(in=FSS5, out=sout7);
 HalfAdder(a=sout7, b=sout6, sum=FHSS5, carry=FHCS5);
 HalfAdder(a=FHSS5, b=FFHCS4, sum=s[5], carry=FHHCS5);

 And(a=a[3], b=b[3], out=a3b3);
 DFF(in=FCS5, out=sout8);
 DFF(in=a3b3, out=sout9);
 HalfAdder(a=sout9, b=sout8, sum=HSS6, carry=HCS6);
 FullAdder(a=HSS6, b=FHCS5, c=FHHCS5, sum=s[6], carry=HFCS6);

 HalfAdder(a=HCS6, b=HFCS6, sum=s[7], carry=carry);
}

运行结果

超级流水线

"超级流水线"技术(Super Pipelining)
将五级流水线细分为更多的阶段, 增加流水线的深度
提升时钟频率,从而提高指令吞吐率

五级流水线:S1 S2 S3 S4 S5
时钟周期: 200ps+50ps=250ps
单条指令的延迟: 1250ps
流水线寄存器延迟所占比例: 50ps / 250ps = 20%
十级流水线:S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
时钟周期: 100ps+5Ops=150ps
单条指令的延迟: 1500ps
流水线寄存器延迟所占比例: 50ps I 150ps = 33%

超标量流水线

超标量(Super scalar)
通常, 具有两条或两条以上并行工作的流水线结构称为超标量结构

亦称为"超标量流水线"或直接称为"超标量"
与之相对,之前的流水线则称为"标量流水线"
使用超标量结构的处理器称为超标量处理器

流水线的"冒险"

流水线处理机的相关
因为流水线中指令和数据要提前取出来, 因此相邻指令之间存在许多关联.
相关概念:相近指令间出现了某种关联, 使得指令不能提前解释
结构相关:由于硬件资源不足而导致流水线不畅通.
数据相关:本条指令的操作数地址与前一条指令存放结果的地址相同, 便出现了前条指令还没有结果, 而后一条指令要求提前取出, 造成错误.
转移相关:由于在转移发生之前, 若干条转移指令的后继指令已被取到流水线处理机中, 而造成错误.

阻止下一条指令在下一个时钟周期开始执行的情况

结构冒险
所需的硬件部件正在为之前的指令工作
数据冒险
需要等待之前的指令完成数据的读写
控制冒险
需要根据之前指令的结果决定下一步的行为

结构冒险(实例1)

如果指令和数据放在同一一个存储器中, 则不能同时读存储器
解决方案1 :流水线停顿( stall), 产生空泡( bubble )

解决方案2 :指令和数据放在不同的存储器中

结构冒险(实例2)

如果读寄存器和写寄存器同时发生,如何处理?
解决方案:前半个时钟周期写, 后半个时钟周期读, 并且设置独立的读写口

数据冒险(实例1)

一条指令需要使用之前指令的运算结果, 但是结果还没有写回
解决方案1 :流水线停顿( stall), 产生空泡( bubble )

控制冒险(实例1)

尚未确定是否发生分支, 如何进行下一-次取指?
解决方案1 :流水线停顿( stall), 产生空泡( bubble )

Hack机器语言

Hack是一个16位计算机, 采用哈佛结果(一种将程序指令存储和数据存储分开的存储器).由⼀个 CPU/两个独⽴的32K内存空间(指令内存和数据内存,都是16位宽,15位地址空间),以及两个内存映射 I/O 设备组成(显示器和键盘,位于 0x4000和0x6000).其 CPU 中的寄存器只有两个:D 和 A 寄存器,D ⽤来存储数据值,A 既可以作为数据寄存器也可以作为地址寄存器.最后,Hack ⽤助记符 M 表示内存.

Hack计算机

数据存储器: RAM, 以下用M表示
程序存储器: ROM, 指令在其中
程序计数器: PC
寄存器: D/A
指令集: 只包含两条指令
- A指令(Addressing Instruction)
- C指令(Compute Instruction)

A指令

A指令的符号表示

@value

value 是一个非负的十进制或者一个代表数值的符号
上述数值进入A寄存器(value->A)

A指令的用法实例

将常数输⼊计算机(⽴即数寻址)
指定⽬标内存单元的地址(直接寻址, 寻址32K数据内存)
指定跳转⽬的指令地址(寻址32K指令内存)

@17     // A = 17
D = A   // D = 17

@17     // A = 17
D = M   // D = RAM[17]

@17     // A = 17
JMP     // 跳到ROM[17]的位置

表示

0xxx xxxx xxxx xxxx

其⾸位为0是操作码, 后15位是操作数.

C指令

dest = comp; jump

dest 和jump域都可以为空
如果dest为空, 则'='被省略
如果jump为空, 则';'被省略

C指令是Hack平台程序的重点, 它描述了
1. 计算什么
2. 将计算结果存到哪里
3. 下一步做什么

其格式是:

dest = comp ; jump

其中dest描述运算结果(ALU 的输出,如果dest为空则'='号省略)存放位置; comp告诉ALU计算什么;jump描述转移条件(如果jump为空,则;号省略).

C指令二进制格式是:

1 1 1 a cl c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3

其⾸位为1(以此与A指令相区别),是操作码;后15位是操作数,其中头两位未定义,可设为1;从a到c6是comp 域;从d1到d3是dest域;从j1到j是 jump域.

comp助记符

c1	c2	c3	c4	c5	c6	助记符(a=0时)	助记符(a=1时
1	0	1	0	1	0	0
1	1	1	1	1	1	1
1	1	1	0	1	0	-1
0	0	1	1	0	0	D
1	1	0	0	0	0	A	M
0	0	1	1	0	1	!D
1	1	0	0	0	1	!A	!M
0	0	1	1	1	1	-D
1	1	0	0	1	1	-A	-M
0	1	1	1	1	1	D+1
1	1	0	1	1	1	A+1	M+1
0	0	1	1	1	0	D-1
1	1	0	0	1	0	A-1	M-1
0	0	0	0	1	0	D+A	D+M
0	1	0	0	1	1	D-A	D-M
0	0	0	1	1	1	A-D	M-D
0	0	0	0	0	0	D&A	D&M
0	1	0	1	0	1	D	A

C 指令中 dest 域的含义

d1(A)	d2(D)	d3(M)	助记符	解释
0	0	0		该值不会被存储
0	0	1	M	RAM[A]内存单元的地址有寄存器A给出
0	1	0	D	D寄存器
0	1	1	DM	D寄存器和RAM[A]
1	0	0	A	A寄存器
1	0	1	AM	A寄存器和RAM[A]
1	1	0	AD	A寄存器和D寄存器
1	1	1	ADM	A寄存器/D寄存器/ARM[A]

上表说明, d1/d2/d3 位分别决定 ALU 结果是否写回 A/D 寄存器或数据存储器 M(表示为 RAM[A])

C 指令 jump 域的含义是

j1 (out < 0)	j2 (out=0)	j3 (out>0)	助记符	解释
0	0	0		不跳转
0	0	1	JGT	如果输出大于零则跳转
0	1	0	JEQ	如果输出等于零则跳转
0	1	1	JGE	如果输出大于等于零则跳转
1	0	0	JLT	如果输出小于零则跳转
1	0	1	JNE	如果输出不等于零则跳转
1	1	0	JLE	如果输出小于等于零则跳转
1	1	1	JMP	无条件跳转(直接跳转)

CPU局部结构图

107

程序范例

条件分支

if RAM[3] == 5 then
goto 100
else
goto 200
end

@3
D = M // D = RAM[3]
@5 // A = 5
D = D - A // D = D - 5
@100
D; JEQ // 如果 D 为零则跳转到100指令地址处
@200
0; JMP // 无条件跳转到200指令地址处, '0'这个 ALU 操作不会影响跳转

循环语句

@i // i 指代某个内存单元, 其地址由汇编程序赋予, 这一句是把 i 的地址装入 A 寄存器
M = 1 // A 寄存器对应的内存单元赋值为1, 即 i = 1
@sum // sum 指代某个内存单元
M = 0 // sum = 0
(LOOP) // 标签, 其值为下一条指令的地址
@i
D = M // D = i
@100
D = D - A // D = i - 100
@END
D; JGT // 如果 (i-100)>0 跳转到 END
@i
D = M // D = i
@sum
M = D + M // sum = sum + i
@i
M = M + 1 // i = i + 1
@LOOP
0; JMP // 无条件跳转
(END)
@END
0; JMP // 无条件跳转, 程序将在这两条指令处无限循环

创建变量x, 并赋初值5

// 1. 创建变量x, 并赋初值5
@5
D = A
@x //汇编器给变量 x 指定的内存单元是16号单元, 如下图所示
M = D

无条件转移

// 2. 无条件转移
// 跳转到20号地址
@20
0;JMP

向内存单元写数据

// 3. 向内存单元写数据
@30 // 向内存单元[30]写数据
M = D

从内存单元读数据

// 4. 从内存单元读数据
// 在CPU仿真器中修改20号内存单元数值, 执行程序观察D寄存器变化
@20 // 从内存单元[20]读数据
D = M

读按键值

// 5. 读按键值
// 读按键值存入D寄存器.该程序是一个无限循环, 在仿真器里运行后按键盘按键观察D寄存器数值
(LOOP)
@KBD
D = M
@LOOP
0;JMP

绘制屏幕

// 6. 绘制屏幕
// 在Hack计算机屏幕左上⻆绘制横线.在CPU仿真器里运行程序观察结果.
@255
D = A
@16384
M = D

顺序结构程序设计

// 7. 顺序结构程序设计
// 计算 c = a + b
// 初始化, a = 1
@a
M = 1
// 初始化, b = 5
@5
D = A
@b
M = D
// 计算.a的值在D中, b的值在M中, ALU做 D+M 结果写回D寄存器
@a
D = M
@b
D = D + M
// 计算结果写入c
@c
M = D
// 程序的正确结束方式
(END)
@END
0;JMP

选择分支结构程序设计

// 8. 选择分支结构程序设计
// if D > 0:
// x = 1
// else:
// x = -1
@TRUE
D;JGT
@x
M = -1
@END
0;JMP
(TRUE) // TRUE 和下面的 END 是标号, 由汇编器计算指令地址
@x
M = 1
(END)
@END
0;JMP

循环结构程序设计

// 9. 循环结构程序设计
// n = 10
// while n > 0:
// n = n-1
@10
D = A
@n
M = D
(LOOP)
@n
D = M
@END
D;JLE
@n
M = M - 1
@LOOP
0;JMP
(END)
@END
0;JMP

设计开发

mult

真值表

RAM[0]	RAM[1]	RAM[2]
0	0	0
1	0	0
0	2	0
3	1	3
2	4	8
6	7	42

代码实现

// 计算R2=R1*R1
// 思路: 循环套加法
// R0和R2相加, 循环次数位R1

@R2
M=0

@i
M=0

@R1
D=M
@LOOP
D;JGT

@R0
M=-M
@R1
M=-M

(LOOP)
@i
D=M
@R1
D=D-M
@END
D;JGE

@i
M=M+1
@R0
D=M
@R2
M=D+M
@LOOP
0;JMP

(END)
@END
0;JMP

运行结果

119

fill

真值表

RAM[16384]	RAM[17648]	RAM[18349]	RAM[19444]	RAM[20771]	RAM[21031]	RAM[22596]	RAM[23754]	RAM[24575]
0	0	0	0	0	0	0	0	0
-1	-1	-1	-1	-1	-1	-1	-1	-1
0	0	0	0	0	0	0	0	0

代码实现

(LOOP)
@24576
D=M

@WHITEINIT
D;JEQ

@i
M=0

@8191
D=A
@N
M=D

@16384
D=A
@addr
M=D

(BLACK)
@i
D=M
@N
D=D-M
@END
D;JGT

D = -1 // 横线
// D = 1   // 竖线

@addr
A=M

M=D

@i
M=M+1
@addr
M=M+1

@BLACK
0;JMP

(WHITEINIT)
@i
M=0

@8191
D=A
@N
M=D

@16384
D=A
@addr
M=D

(WHITE)
@i
D=M
@N
D=D-M
@END
D;JGT

D=0

@addr
A=M

M=D

@i
M=M+1
@addr
M=M+1

@WHITE
0;JMP

(END)
@LOOP
0;JMP

运行结果

120

寻址

121

@20    // 寻址方式
    EA=X
    data=20
D=A    // 寻址方式, D=20
    EA=X
    data=20
D=M    // 寻址方式, D=RAM[20]的值
    EA=20
    data=RAM[20]

MOV AX, BX
MOV AX, [BX]
MOV AX, 100[BX]

立即数寻址

所需的操作数由指令的直接给出, 称为立即数寻址方式, 简称立即寻址.

108

这种方式的特点是:

取指令时将操作码和一个操作数同时取出, 不必再次访问存储器.提高了指令的执行速度.

例子

119

这条指令的执行结果是"把立即数1536传送到目的寄存器Ri中"

Hack符号
@23

汇编符号
MOV Ri#, 1536

操作数S与寄存器Ri之间的关系是: S=1536

直接寻址

直接寻址是指指令中的地址码就是操作数的有效地址, 按这个地址可直接在存储器中存入或取得操作数.

110

采用直接寻址方式时, 指令字中的形式地址D就是操作数的有效地址E, 既E=D.因此通常把形式地址D又称为直接地址.此时, 由寻址模式给予指示, 如X1=0.如果用S表示操作数, 那么直接寻址的逻辑表达式为:

S= (EA) = (D) = (A) (教材用A代表有效地址或形式地址)

hack符号
@10
D=M

汇编符号
MOV Ri, (D)

例子

111

图中特性码X1指明是采用直接寻址

该指令表示 "把1536号存储单元中存放的操作数153400取出,送入存器Ri中"

直接地址也可以用公式表示, 若设有效地址为EA,则可记为:

当X1=0时, EA=D(D就是有效地址)

间接寻址

指令中的地址码部分给出的既不是操作数, 又不是操作数的地址, 而是存放操作数地址的内存单元的地址, 这个地址叫做间接地址.其寻址方式称为间接寻址方式, 简称间址.

112

通常在间接寻址情况下, 由寻址特征位给予指示, 如X2=1或@(教材上)

S= ((EA))= ((D))=((A)) (教材用A代表有效地址或形式地址)

Hack符号
@16
A=M
D=M

例子

113

寄存器直接寻址

如果指令的地址码部分给出的是某通用寄存器编号Ri, Ri寄存器中存放着操作数, 则称为寄存器直接寻址.

S=(Ri)

114

Hack符号
@20
D=A; D=20

汇编符号
MOV AX, BX; BX=2000, AX=2000

寄存器间接寻址

寄存器间接寻址, 是指令中地址字段所指的寄存器中存放的是操作数的地址.

例如:执行ADD @Ri指令时,说明Ri不是操作数的有效地址,而是存放操作有效地址的寄存器号.

115

操作数不是在寄存器中, 而是操作数的所在内存地址在寄存器中

S=((Ri))

@20
D=M

变址寻址方式

变址寻址是将指令中的基地址码和一一个"变址值"相加后形成操作数的有效地址."变址值"存放在一个专用的变址寄存器Ri中或专用的内存单元中.

变址值是根据程序需要而设置的, 与本条指令中的地址长度无关, 只要变址寄存器的字长足够长, 可以进行内存全容量的访问.使用起来十分灵活.

S=((Rx)+A) Rx是变址寄存器A形式地址

116

基址寻址方式

当存储容量较大, 所需地址码的长度大于字长时, 指令中的地址码部分直接给出的地址不可能直接访问存储器的所有单元.因此, 把整个存储空间分成若干段, 每段的首地址存放在一个基址寄存器中, 段内的位移量由指令直接给出. 于是, 存储器的实际地址就等于基址寄存器的内容加上段内位移量.这就叫做基址寄存器寻址方式, 简称基址寻址.

117

S=((Rb)+D) Rb是基址寄存器D是位移量

相对寻址

相对寻址是把程序计数器PC的内容加上指令格式中的形式地址D而形成操作数的有效地址.

程序计数器的内容就是当前指令的地址."相对"寻址, 就是相对于当前的指令地址而言.

此时形式地址D通常称为偏移量, 其值可正可负, 相对于当前指令地址进行浮动.

118

S=(PC)+D PC程序计数器D 位移量

屏幕显示字符"新"

122

代码实现

// '新'的字形码:[8, 8208, 7934, 512, 580, 552, 32511, 4624, 4624, 4862, 4624, 4692, 4754, 4369, 4372, 4232]
// 字形码载入内存
@8
D = A
@16
M = D

@8208
D = A
@17
M = D

@7934
D = A
@18
M = D

@512
D = A
@19
M = D

@580
D = A
@20
M = D

@552
D = A
@21
M = D

@32511
D = A
@22
M = D

@4624
D = A
@23
M = D

@4624
D = A
@24
M = D

@4862
D = A
@25
M = D

@4624
D = A
@26
M = D

@4692
D = A
@27
M = D

@4754
D = A
@28
M = D

@4369
D = A
@29
M = D

@4372
D = A
@30
M = D

@4232
D = A
@31
M = D

// 主程序
@SCREEN
D = A
@p     // 初始化指针 p = SCREEN
M = D

@16
D = A
@q     // q 指针指向字形码头部
M = D

@16    // R0 保存循环变量
D = A
@R0
M = D

(LOOP)
@q
A = M
D = M

@p
A = M
M = D

@32
D = A

@p
M = M + D

@q
M = M + 1

@R0
M = M - 1
D = M

@END
D;JEQ

@LOOP
0; JMP

// 程序结束
(END)
@END
0;JMP

运行结果

中央处理器

CPU(中央处理器:运算器+控制器组成.)
运算器:算数运算和逻辑运算
控制器:对指令译码, 并产生相应的控制信号

冯诺依曼结构

冯诺依曼体系结构的基础是一个中央处理单元(CPU, Central Processing Unit), 它与记忆设备(memory device)即内存进行交互, 负责从输入设备(input device)接收数据, 向输出设备(output device) 发送数据.这个体系结构的核心是存储程序的概念:计算机内存不仅存储着要进行操作的数据, 还存储着指示计算机运行的指令.
128

指令系统

分析指令系统,得出对数据通路的需求

为数据通路选择合适的组件
连接组件建立数据通路
分析每条指令的实现, 以确定控制信号
集成控制信号,形成完整的控制逻辑
算术逻辑单元( ALU)
- 运算类型:加/减或比较相等
- 操作数: 2个32位的数,来自寄存器或扩展后的立即数
程序计数器(PC)
- 一个32位的寄存器
- 支持两种加法:加4或加一个立即数

Memory(数据内存)

131
Hack的数据内存地址总线宽度为15位, 能够寻址32K地址空间, 该内存空间在Hack计算机中被划分成了三部分:前16K空间是通常所指的内存, 用芯片RAM16K表示;从16384 ~ 24575 (0x4000 ~ 0xFFFF)的8K地址空间是显示器Screen的/0映射; 24576 (0x6000) 这个单个内存空间是键盘Keyboard的I/0映射.读/写0x6000以上地址的内存都是无效的.
Memory芯片的读操作是:芯片的输出始终是当前地址所指向内存单元的值.写操作有时序性, 具体是:在上个时钟周期输入数据和地址, 然后置位load信号, 在当前时钟周期开始时数据被写入特定内存单元.
Memory芯片包含的三个芯片的接口如下:

130

132
可以看到RAM16K和Screen的接口-样,特别是Screen,对其操作和对一般内存的操作是一样的, 这是I/O映射的特点--设备看上去就像普通的内存一样. 键盘Keyboard芯片的接口较为不同,可以看到它只有输出端, 即当做只读设备.

真值表

in	load	address	out
-1	1	000000000000000	0
-1	1	000000000000000	-1
9999	0	000000000000000	-1
9999	0	000000000000000	-1
9999	0	010000000000000	0
9999	0	100000000000000	0
2222	1	010000000000000	0
2222	1	010000000000000	2222
9999	0	010000000000000	2222
9999	0	010000000000000	2222
9999	0	000000000000000	-1
9999	0	100000000000000	0
9999	0	000000000000001	0
9999	0	000000000000010	0
9999	0	000000000000100	0
9999	0	000000000001000	0
9999	0	000000000010000	0
9999	0	000000000100000	0
9999	0	000000001000000	0
9999	0	000000010000000	0
9999	0	000000100000000	0
9999	0	000001000000000	0
9999	0	000010000000000	0
9999	0	000100000000000	0
9999	0	001000000000000	0
9999	0	010000000000000	2222
1234	1	001001000110100	0
1234	1	001001000110100	1234
1234	0	010001000110100	0
1234	0	110001000110100	0
2345	1	010001101000101	0
2345	1	010001101000101	2345
2345	0	000001101000101	0
2345	0	100001101000101	0
2345	0	110000000000000	75
-1	1	100111111001111	-1
-1	1	101000001001111	-1
-1	1	000111111001111	0
-1	1	010111111001111	0
-1	0	100111111001110	0
-1	0	100111111001101	0
-1	0	100111111001011	0
-1	0	100111111000111	0
-1	0	100111111011111	0
-1	0	100111111101111	0
-1	0	100111110001111	0
-1	0	100111101001111	0
-1	0	100111011001111	0
-1	0	100110111001111	0
-1	0	100101111001111	0
-1	0	100011111001111	0
-1	0	101111111001111	0
-1	0	110000000000000	89

代码实现

CHIP Memory {
    IN in[16], load, address[15];
    OUT out[16];

    PARTS:
    DMux(in = load, sel = address[14], a = loadR, b = loadS);
    Mux4Way16(a = outR, b= outR, c= outS, d= kbd, sel = address[13..14], out = out);
    RAM16K(in = in, load = loadR, address = address[0..13], out = outR);
    Screen(in = in, load = loadS, address = address[0..12], out = outS);
    Keyboard(out = kbd);
}

CPU

构建完整的CPU是整个硬件设计中最难啃的部分, 下图展示了该芯片的接口

129

127
在上图中控制信号都标注了c, 已知的一些控制信号比如ALU的c1 ~ c6建议采用其原本的名字,其它控制信号比如D寄存器的load端命名为Dload.这样一来, 大家就可以在相同的命名方式下讨论设计了.
上图中应该引起你注意的是decode这个部分, 它不是一个曾经构建过的芯片, 它的功能相当于冯诺依曼结构中的控制器(Controller) .图中显示, 它的输入是指令(instruction) , 输出是控制信号.通过分析指令, 控制器产生-组合适的控制信号实现特定操作.如果把指令的各部分按下图命名

i	x	x	a	c1	c2	c3	c4	c5	c6	d1	d2	d3	j1	j2	j3

将首位命名为i, 则当i=0时, 指令是A指令,此时指令的低15位应全部载入A寄存器的对应位置(最高位置零).为了实现该操作, 需要控制信号的配合,打通一条合适的数据通路(data-path) .

真值表

time	inM	instruction	reset	outM	writeM	addre	pc	DRegiste
0+	0	0011000000111001	0	*******	0	0	0	0
1	0	0011000000111001	0	*******	0	12345	1	0
1+	0	1110110000010000	0	*******	0	12345	1	12345
2	0	1110110000010000	0	*******	0	12345	2	12345
2+	0	0101101110100000	0	*******	0	12345	2	12345
3	0	0101101110100000	0	*******	0	23456	3	12345
3+	0	1110000111010000	0	*******	0	23456	3	11111
4	0	1110000111010000	0	*******	0	23456	4	11111
4+	0	0000001111101000	0	*******	0	23456	4	11111
5	0	0000001111101000	0	*******	0	1000	5	11111
5+	0	1110001100001000	0	11111	1	1000	5	11111
6	0	1110001100001000	0	11111	1	1000	6	11111
6+	0	0000001111101001	0	*******	0	1000	6	11111
7	0	0000001111101001	0	*******	0	1001	7	11111
7+	0	1110001110011000	0	11110	1	1001	7	11110
8	0	1110001110011000	0	11109	1	1001	8	11110
8+	0	0000001111101000	0	*******	0	1001	8	11110
9	0	0000001111101000	0	*******	0	1000	9	11110
9+	11111	1111010011010000	0	*******	0	1000	9	-1
10	11111	1111010011010000	0	*******	0	1000	10	-1
10+	11111	0000000000001110	0	*******	0	1000	10	-1
11	11111	0000000000001110	0	*******	0	14	11	-1
11+	11111	1110001100000100	0	*******	0	14	11	-1
12	11111	1110001100000100	0	*******	0	14	14	-1
12+	11111	0000001111100111	0	*******	0	14	14	-1
13	11111	0000001111100111	0	*******	0	999	15	-1
13+	11111	1110110111100000	0	*******	0	999	15	-1
14	11111	1110110111100000	0	*******	0	1000	16	-1
14+	11111	1110001100001000	0	-1	1	1000	16	-1
15	11111	1110001100001000	0	-1	1	1000	17	-1
15+	11111	0000000000010101	0	*******	0	1000	17	-1
16	11111	0000000000010101	0	*******	0	21	18	-1
16+	11111	1110011111000010	0	*******	0	21	18	-1
17	11111	1110011111000010	0	*******	0	21	21	-1
17+	11111	0000000000000010	0	*******	0	21	21	-1
18	11111	0000000000000010	0	*******	0	2	22	-1
18+	11111	1110000010010000	0	*******	0	2	22	1
19	11111	1110000010010000	0	*******	0	2	23	1
19+	11111	0000001111101000	0	*******	0	2	23	1
20	11111	0000001111101000	0	*******	0	1000	24	1
20+	11111	1110111010010000	0	*******	0	1000	24	-1
21	11111	1110111010010000	0	*******	0	1000	25	-1
21+	11111	1110001100000001	0	*******	0	1000	25	-1
22	11111	1110001100000001	0	*******	0	1000	26	-1
22+	11111	1110001100000010	0	*******	0	1000	26	-1
23	11111	1110001100000010	0	*******	0	1000	27	-1
23+	11111	1110001100000011	0	*******	0	1000	27	-1
24	11111	1110001100000011	0	*******	0	1000	28	-1
24+	11111	1110001100000100	0	*******	0	1000	28	-1
25	11111	1110001100000100	0	*******	0	1000	1000	-1
25+	11111	1110001100000101	0	*******	0	1000	1000	-1
26	11111	1110001100000101	0	*******	0	1000	1000	-1
26+	11111	1110001100000110	0	*******	0	1000	1000	-1
27	11111	1110001100000110	0	*******	0	1000	1000	-1
27+	11111	1110001100000111	0	*******	0	1000	1000	-1
28	11111	1110001100000111	0	*******	0	1000	1000	-1
28+	11111	1110101010010000	0	*******	0	1000	1000	0
29	11111	1110101010010000	0	*******	0	1000	1001	0
29+	11111	1110001100000001	0	*******	0	1000	1001	0
30	11111	1110001100000001	0	*******	0	1000	1002	0
30+	11111	1110001100000010	0	*******	0	1000	1002	0
31	11111	1110001100000010	0	*******	0	1000	1000	0
31+	11111	1110001100000011	0	*******	0	1000	1000	0
32	11111	1110001100000011	0	*******	0	1000	1000	0
32+	11111	1110001100000100	0	*******	0	1000	1000	0
33	11111	1110001100000100	0	*******	0	1000	1001	0
33+	11111	1110001100000101	0	*******	0	1000	1001	0
34	11111	1110001100000101	0	*******	0	1000	1002	0
34+	11111	1110001100000110	0	*******	0	1000	1002	0
35	11111	1110001100000110	0	*******	0	1000	1000	0
35+	11111	1110001100000111	0	*******	0	1000	1000	0
36	11111	1110001100000111	0	*******	0	1000	1000	0
36+	11111	1110111111010000	0	*******	0	1000	1000	1
37	11111	1110111111010000	0	*******	0	1000	1001	1
37+	11111	1110001100000001	0	*******	0	1000	1001	1
38	11111	1110001100000001	0	*******	0	1000	1000	1
38+	11111	1110001100000010	0	*******	0	1000	1000	1
39	11111	1110001100000010	0	*******	0	1000	1001	1
39+	11111	1110001100000011	0	*******	0	1000	1001	1
40	11111	1110001100000011	0	*******	0	1000	1000	1
40+	11111	1110001100000100	0	*******	0	1000	1000	1
41	11111	1110001100000100	0	*******	0	1000	1001	1
41+	11111	1110001100000101	0	*******	0	1000	1001	1
42	11111	1110001100000101	0	*******	0	1000	1000	1
42+	11111	1110001100000110	0	*******	0	1000	1000	1
43	11111	1110001100000110	0	*******	0	1000	1001	1
43+	11111	1110001100000111	0	*******	0	1000	1001	1
44	11111	1110001100000111	0	*******	0	1000	1000	1
44+	11111	1110001100000111	1	*******	0	1000	1000	1
45	11111	1110001100000111	1	*******	0	1000	0	1
45+	11111	0111111111111111	0	*******	0	1000	0	1
46	11111	0111111111111111	0	*******	0	32767	1	1

代码实现

CHIP CPU {

    IN  inM[16], instruction[16], reset;

    OUT outM[16], writeM, addressM[15], pc[15];

    PARTS:
    Controller(i = instruction[15], d1 = instruction[5], d2 = instruction[4], d3 = instruction[3],
                j1 = instruction[2], j2 = instruction[1], j3 = instruction[0], zr = zr0, ng = ng0,
                Asel = Asel, Aload = Aload, Dload = Dload, WriteM = writeM, PCinc = PCinc, PCload = PCload);

    Mux16(a = outM0, b[15] = false, b[0..14] = instruction[0..14], sel = Asel, out = Ain);

    ARegister(in = Ain, load = Aload, out = Aout, out[0..14] = Apc, out[0..14] = addressM);

    Mux16(a = Aout, b = inM, sel = instruction[12], out = AM);

    DRegister(in = outM0, load = Dload, out= D);

    ALU(x= D, y= AM, zx = instruction[11], nx = instruction[10], zy = instruction[9], ny = instruction[8],
        f= instruction[7], no = instruction[6], out = outM0, out = outM, zr = zr0, ng = ng0);

    PC(in[15] = false, in[0..14] = Apc, load = PCload, inc = PCinc, reset = reset, out[0..14] = pc);
}

Controller

134
其输入端不仅有指令中所有的域, 还有ALU的状态输出位: zr 和ng,原因是你需要根据ALU的这两个输出和j1~j3来决定如何更新程序计数器PC的值, 即产生正确的load信号.控制器的输出端有CPU接口图中标注的所有控制信号, 中c1 ~ c6在输入端时含义是指令中的位, 在输出端时含义是CPU中的控制信号, 它们名称-致暗
示是直连的关系.
实现上述控制器最困难的部分是产生load的逻辑, 建议你以i,j1, j2, j3, zr, ng为输入, 以load为输出建立真值
表, 仔细分析其中的逻辑关系, 写出对应逻辑表达式.
当实现复杂的逻辑关系的时候, 要本着化繁为简的思想.根据Boole's expansion理论
f(1,j2,js, Zr, Ng) = j1f(1,j2,js, Zr,Ng) + j1f(0,j2,js, Zr,Ng)
即原来含有5个逻辑变量的逻辑表达式可以分解成两个仅含4个逻辑变量的表达式, 减少的那个逻辑变量在子表达式
里取常数0或1.实现上式的时候用到了数据选择器, 如下图所示

135

代码实现

CHIP Controller {
    IN i, d1, d2, d3, j1, j2, j3, zr, ng;
    OUT Asel, Aload, Dload, WriteM, PCinc, PCload;
    PARTS:
    Or(a = d1, b = iNg, out = Aload);
    Not(in = i, out = iNg, out = Asel);

    And(a = i, b = d2, out = Dload);
    And(a = i, b = d3, out = WriteM);

    Not(in = j1, out = j1N);
    Not(in = j2, out = j2N);
    Not(in = j3, out = j3N);

    Not(in = zr, out = zrN);
    Not(in = ng, out = ngN);
    And4(a = j1N, b = j3, c = zrN, d = ngN, out = l1);
    And4(a = j1N, b = j2, c = j3, d = ngN, out = l2);
    And4(a = j2, b = true, c = zr, d = ngN, out = l3);
    And4(a = j1, b = j2, c = j3, d = true, out = l4);
    And4(a = j1, b = zrN, c = true, d = ng, out = l5);
    And4(a = j1, b = true, c = j3, d = zrN, out = l6);

    Or(a = l1, b= l2, out = o1);
    Or(a = l3, b= l4, out = o2);
    Or(a = l5, b= l6, out = o3);
    Or(a = o1, b= o2, out = o4);
    Or(a = o3, b= o4, out = pcload0);
    And(a = pcload0, b = i, out = pcload1, out = PCload);

    Not(in = pcload1, out = pcload2);
    And(a = pcload2, b = true, out = PCinc);
}

Computer

133

代码实现

CHIP Computer {
    IN reset;

    PARTS:
    CPU(inM = outM, instruction = outR, reset = reset, outM = inMem, writeM = loadM, addressM = addressMem, pc = addressR);
    Memory(in = inMem, load = loadM, address = addressMem, out = outM);
    ROM32K(address = addressR, out = outR);
}

运行结果

136
137
138
139
140
141
142
143
144
136

参考资料

标签：计算机,16,21845,21846,笔记,0000000000000000,原理,sel,out
From： https://www.cnblogs.com/Ahtelek/p/16841867.html

in	sel	a	b	c	d	e	f	g	h
0	000	0	0	0	0	0	0	0	0
0	001	0	0	0	0	0	0	0	0
0	010	0	0	0	0	0	0	0	0
0	011	0	0	0	0	0	0	0	0
0	100	0	0	0	0	0	0	0	0
0	101	0	0	0	0	0	0	0	0
0	110	0	0	0	0	0	0	0	0
0	111	0	0	0	0	0	0	0	0
1	000	1	0	0	0	0	0	0	0
1	001	0	1	0	0	0	0	0	0
1	010	0	0	1	0	0	0	0	0
1	011	0	0	0	1	0	0	0	0
1	100	0	0	0	0	1	0	0	0
1	101	0	0	0	0	0	1	0	0
1	110	0	0	0	0	0	0	1	0
1	111	0	0	0	0	0	0	0	1

c1	c2	c3	c4	c5	c6	助记符(a=0时)	助记符(a=1时
1	0	1	0	1	0	0
1	1	1	1	1	1	1
1	1	1	0	1	0	-1
0	0	1	1	0	0	D
1	1	0	0	0	0	A	M
0	0	1	1	0	1	!D
1	1	0	0	0	1	!A	!M
0	0	1	1	1	1	-D
1	1	0	0	1	1	-A	-M
0	1	1	1	1	1	D+1
1	1	0	1	1	1	A+1	M+1
0	0	1	1	1	0	D-1
1	1	0	0	1	0	A-1	M-1
0	0	0	0	1	0	D+A	D+M
0	1	0	0	1	1	D-A	D-M
0	0	0	1	1	1	A-D	M-D
0	0	0	0	0	0	D&A	D&M
0	1	0	1	0	1	D	A

in	sel	a	b	c	d	e	f	g	h
0	000	0	0	0	0	0	0	0	0
0	001	0	0	0	0	0	0	0	0
0	010	0	0	0	0	0	0	0	0
0	011	0	0	0	0	0	0	0	0
0	100	0	0	0	0	0	0	0	0
0	101	0	0	0	0	0	0	0	0
0	110	0	0	0	0	0	0	0	0
0	111	0	0	0	0	0	0	0	0
1	000	1	0	0	0	0	0	0	0
1	001	0	1	0	0	0	0	0	0
1	010	0	0	1	0	0	0	0	0
1	011	0	0	0	1	0	0	0	0
1	100	0	0	0	0	1	0	0	0
1	101	0	0	0	0	0	1	0	0
1	110	0	0	0	0	0	0	1	0
1	111	0	0	0	0	0	0	0	1

c1	c2	c3	c4	c5	c6	助记符(a=0时)	助记符(a=1时
1	0	1	0	1	0	0
1	1	1	1	1	1	1
1	1	1	0	1	0	-1
0	0	1	1	0	0	D
1	1	0	0	0	0	A	M
0	0	1	1	0	1	!D
1	1	0	0	0	1	!A	!M
0	0	1	1	1	1	-D
1	1	0	0	1	1	-A	-M
0	1	1	1	1	1	D+1
1	1	0	1	1	1	A+1	M+1
0	0	1	1	1	0	D-1
1	1	0	0	1	0	A-1	M-1
0	0	0	0	1	0	D+A	D+M
0	1	0	0	1	1	D-A	D-M
0	0	0	1	1	1	A-D	M-D
0	0	0	0	0	0	D&A	D&M
0	1	0	1	0	1	D	A

计算机组成原理学习笔记