CSC3050 Project 3: RISC-V Simulator

CSC3050 Project 3: RISC-V Simulator with RVV

1 Background RISC-V, an open standard instruction set architecture (ISA), has rapidly become apivotal force in academic research and industrial development due to its flexibilityand open-source nature. Unlike proprietary ISAs, RISC-V offers the freedom fordevelopers to customize and extend the architecture, making it an ideal platformfor innovation in research, education, and the design of specialized hardware. Oneof its most impactful extensions is the RISC-V Vector Extension (RVV), whichintroduces efficient vector processing capabilities—a cornerstone of modern highperformancecomputing. This is especially critical for applications like machinlearning, cryptography, and scientific simulations, where parallel data processing is

implementing some of the RVV instructions.After reviewing the number of cycles, you will get a feeling of how this is fasterthan conducting element-wise operations.Start early, this project can be time-consuming if you are not familiar withsimulators.

2 QTRVSim

QTRVSim is a RISC-V CPU simulator for education, where you can try its online

version on this link. Just in case you want to try different instructions, you can refer

to this page: RISC-V Instruction Set Specifications. A helpful video about usingQTRVSim can be found on YoutubeAfter familiarizing yourself with the QtRVSim manual, you can begin planning howto integrate RVV instructions into the existing implementation. The simulator’ssource code, written in C++ and including both the core simulation functions andgraphical user interfaces (GUIs), can be found in the repository at this link. To testyour modifications, QtRVSim offers two methods for simulating assembly code: GUIor command-line prompts.

Note: For this project, you are not required to modify any of the GUI components.Your primary goal is to ensure that the RVV instructions function correctly whenusingcommand-line prompts. Another objective in this project is to save the number

of cycles; the smaller the number you get, the better the score you get.

12.1 How to run We give the example of running QTRVSim on Ubuntu with the terminal. You canfollow these steps:We assume you already have the necessary packages for compiling cpp. Inot, you can easily find tutorial for them on the internet.Install QT6 (QT5 does not work in most cases) with sudo apt install qt6-

-dev. You might need sudo apt update first, and make sure you areinstalling QT6, not QT5.Download QTRVSim from the given repository.

3. Make a new directory for building files (mkdir build; cd build)
4. cmake -DCMAKE BUILD TYPE=Release /path/to/qtrvsim
5. make -j X, where X is the number of threads you want to use
6. If everything goes correctly, you can use ./target/qtrvsim cli –asm XXXXX.Sto run your .S file.

8. Via ./target/qtrvsim cli –help, you can check all helpful arguments.

3 RVV Instructions

In this assignment, you are required to implement the following RVV instructions

(suppose max vector size is 32):

1. vsetvl rd, rs1, rs2: sets the length register vl to rs1 and rd, also sets the

register holding the type of vector to rs2 (8/16/32).

2. vadd.vv vd, vs2, vs1: adds two vectors vs2 and vs1, and stores the resultin vd

3. vadd.vx vd, vs2, rs1: adds rs1 to each element of vector vs2, and storesthe result in vd vadd.vi vd, vs2, imm: adds the scalar value imm to each element of vectorvs2, and stores the result in vd

5. vmul.vv vd, vs2, vs1: conducts dot production on two vectors vs2 and vs1,and stores the result in vd

6. vlw.v vd, (rs1): loads elements stored starting at rs1 into vector vd. Thelength to load is dependent on the length stored at vl and the unit lengthspecified earlier.

7. vsw.v vs3, (rs1): stores vector elements of vs3 into memory starting at rs1.The length to load is dependent on the length stored at vl and the unit lengthspecified earlier.2Figure 1: Matrix stored as vectoThe whole point of this project is that, through the implementation, you willunderstand why are vector operations ismuch faster than manipulate each ele

ment individually. For example, writing 100 elements into memory will require 100individual store instructions if in an element-wise manner. However, using vectorwrite, you only need to do one vector store instruction.代写CSC3050 Project 3: RISC-V Simulator A detailed explanation of RVV instructions can be found at this manual. Reminder: Do not forget to update vl when switching to operate on vectors with differentlengths.4 Matrix Multiplication After implementing and testing the aforementioned functionalities, you are requiredconduct vector multiplication, the size of the matrix n × m will be given.We require you to generate two random matrices with sizes of 20 × 46 and46 × 50 where elements can be of your own choice.

5 Tricks There are several tricks you can apply to reduce cycle counts.

1. Reduction (required): This is similar to calculate the summation of a

vector, but more efficiently. The basic requirement is that you conduct thissummation on each element one-by-one, which leads to excessive cycles.Another approach ido binary split, i.e. repeatedly decompose the a vectorof size n into 2 vectors of size n//2, and then conduct vadd. There are alsoother trick for conducting reduction, andyou can explore any of them.3Possible reduction:(a) scalar loop(b) vector shift

(c) reduction instruction(d) ...

2. Chaining (Extra credit): When conducting vector operations, it is not necessary to wait for the entire instruction to complete. As shown in Figure 2, itis possible to conduct VADD on the first element, right after obtaining thefirst element of VMUL. A much better illustration can be found at Prof.Hsu’sslides at this link.Figure 2: chaining6 Instruction on Implementation The code involved in QTRVSim is quite complicated. Luckily, you only need tofocus on few script files.

1. src/machine/instruction.cpp: Edit this file to add new instructions. The

boxed fields are:

• instruction name
• instruction enum type (you can edit this by yourself; no need to follow

the example)

• input types (you can go through instruction.cpp to see what char is for

what type)

• machine code (hexadecimal)
• mask for effective bits for instruction (hexadecimal)
• customize flags (you can edit this by yourself; no need to follow the

example)

2. src/machine/core.cpp: Main pipeline of the simulator. You can find fetch,

decode, execute, writeback, memory in it, and edit these codes for your con

venience.

43. 4 src/machine/execute/alu.cpp: specify what to do for each alu operation.You can create/edit these codes for your own convenience.instruction.cpp.Notice3: You might want to check dt.num rt, dt.num rd, dt.num rs for specificregister indexing.: The largest vector register length is 32. Load instruction will have amemory latency of 32. Besides, the cycles for multiplication is 4. (This means that,to load a vector of length 10, the total cycles will be 1 + 1 + 32 + 10 + 1 + 1 = 46)

7 Grading Criteria

The maximum score you can get for this lab is 100 points. We will first examine the correctness of your outputs to test cases. Since hard-coding each operation is fairly easy in C++, we will check the execution information, such as thenumber ofcycles, and content in memories/registers. Using of ChatGPT to improve writing/generate codes/provide ideas is allowed and highly-recommended as ChatGPT has become one of the best productivity tools.Conducting ”higher-level” reduction or finishing the task with less number of cycleswill be granted with extra credit.You are also required to compose a report, where you should show the resultof your test case executions. Besides you also need to show the total number ofcycles andexplain where those cycles come from. (few sentences, no need to besuper specific.)The deadline of this project is 23:59, Tuesday, 2024/11/19. For each day aftethe deadline, 10 points will be deducted from your final score up to 30 points, afterwhich you will get 0 pointsBesides, if anyone is interested in developing with QT, you are more than welcometo implement GUI support for RVV instruction. If doneproperly, you will earn extracredits, and might contribute to future contents of this class.eel free to ask questions ifyou find anything confusing.

58 Submission You should make sure your code compiles and runs. Then, it should be compressedinto a .zip file and submitted to BlackBoard. Any necessary instructions tocompile and run your code should also be documented and included. Finally, you arealso required to include a report containing the results of your test case execution.6