DDR4信号测试分类
DDR4信号测试主要分为以下几种情况：
1.以手机为代表的多阶表贴内存颗粒，由于主芯片与内存颗粒几乎是挨着摆放，信号不是通孔，没有测试点，要测试必须使用interposer;
2.以电视为代表的单面表贴颗粒，这种有条件也可以上interposer，没条件就直接刮开过孔、刮开走线绿油测试是一样的。像下面一样，TOP层4mil间距DQS差分焊线，不知道有多少人能做到
3.以PC为代表的UDIMM条，这是最简单的。单面贴的内存条背面都有信号过孔，在过孔处找点测试即可；
4.以Server为代表的服务器RDIMM，包括笔记本的SODIMM，通常都是双面贴颗粒的，也需要用到interposer；
当然还有一种办法，吹掉RDIMM背面的一个颗粒，修改SPD信息，将双面内存修改为单面内存，虽然内存容量降低一半，对于信号测试而言没有什么影响，最重要的是这样就有测试点了，对于主板长走线而言，少一个颗粒的这点分叉影响是微乎其微的，就算上interposer一样也有分叉。亲测有效！
波形读写分离的方法
通过单次触发得到一个读或者写的波形，读的波形是DQS和DQ的相位是基本相同的。写的波形是DQS和DQ的相位基本上是90度。
触发到单个波形之后，通过以下两种方法来看叠加的波形：
1.通过触发到的波形，利用图形触发(Visual Trigger)选定大体的逻辑区域(in或者out)，Kesight示波器是InfiniiScan；
2.通过看读和写的单波形，会发现，读和写DQS的前两个高低电平的宽度是不一样的，使用示波器的宽度(width)触发功能,来触发DQS。
注1：泰克Visual Trigger和是德InfiniiScan都是要单独购买的，这个钱千万不要省，真的非常好用，没有分离不出来的。
注2：DDR3通过前导的正负方向触发读写分离在DDR4无效了，因为DDR4读写前导方向不定，也有可能方向是一样的。
1. DDR4芯片管脚定义描述
DDR4管脚功能描述见下表。
| Symbol |
Type |
Function |
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| CK_t, CK_c |
Input |
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c. |
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| CKE, (CKE1) |
Input |
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t,CK_cS ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self Refresh. |
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| CS_n, (CS1_n) |
Input |
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on systems with multiple Ranks. CS_n is considered part of the command code. |
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| C0,C1,C2 |
Input |
Chip ID : Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code |
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| ODT, (ODT1) |
Input |
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM. |
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| ACT_n |
Input |
Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14 |
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| RAS_n/A16. CAS_n/ |
Input |
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered. Those pins have multi function. For example, for activation with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command pins for Read, Write and other command defined in command truth table |
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| DM_n/DBI_n/ |
Input/Output |
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.Input data is masked when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported in X8 |
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| BG0 - BG1 |
Input |
Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. X4/8 have BG0 and BG1 but X16 has only BG0 |
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| BA0 - BA1 |
Input |
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or |
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| A0 - A17 |
Input |
Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows.The address inputs also provide the op-code during Mode Register Set commands.A17 is only defined for the x4 configuration. |
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| A10 / AP |
Input |
Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. |
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| A12 / BC_n |
Input |
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table fo |