Synopsys 安装记录

安装环境概述

• 系统：win11 的wsl ubuntu18.04
• 软件：芯王国提供的Synopsys2018

完整的安装教程请参考：搭建属于自己的数字IC EDA环境（三）：Centos7安装EDA（vcs2018、verdi2018等）IC工具以及脚本运行第一个工程_scl keygen-CSDN博客

解压遇到的问题

压缩包分卷压缩的，在linux下合并压缩包然后解压报错。直接使用7z在window下解压到linux目录。

安装遇到的问题

运行setup,.sh​

error while loading shared libraries: libXss.so.1​

安装对应的库

sudo apt install libxss1

打开防火墙，激活软件

sudo apt install firewalld
sudo firewall-cmd --zone=public --add-port=27000/tcp --permanent
sudo firewall-cmd --reload

Can't make directory /usr/tmp/.flexlm​

sudo mkdir -p /usr/tmp
sudo touch /usr/tmp/.flexlm

/bin/sh: Illegal option -h​

sudo dpkg-reconfigure dash

-bash: /tools/synopsys2018/scl/2018.06/linux64/bin/lmgrd: No such file or directory​

sudo apt install lsb-core

Failed to open the TCP port number in the license.​

该问题是重复启动lmgrd导致的。

ps auf | grep lmgrd
kill -9 15721   #端口号

​license daemon: system error code: No such file or directory​

修改license文件第二行

修改前

SERVER DESKTOP-UTB5G1J f02f74329738 27000
DAEMON /tools/synopsys2018/scl/2018.06/linux64/bin/snpslmd

修改后

SERVER DESKTOP-UTB5G1J f02f74329738 27000
DAEMON snpslmd /tools/synopsys2018/scl/2018.06/linux64/bin/snpslmd

仿真遇到的问题

/libvcsnew.so: undefined reference to xxx​

参考文献：libvcsnew.so: undefined reference to-CSDN博客

在vcs编译选项后添加-LDFLAGS -Wl,--no-as-needed​即可。

有的还会遇到g++的问题，所以推荐的vcs编译选项如下

-full64 -cpp g++-4.8 -cc gcc-4.8 -LDFLAGS -Wl,--no-as-needed

vcs: line 3312: dc: command not found​

解决方法：command not found_this program is proprietary and confidential infor-CSDN博客

sudo apt install dc

error while loading shared libraries: libpng12.so.0​

参考文献：error while loading shared libraries: libpng12.so.0

wget http://security.ubuntu.com/ubuntu/pool/main/libp/libpng/libpng12-0_1.2.54-1ubuntu1.1_amd64.deb
sudo dpkg -i ./libpng12-0_1.2.54-1ubuntu1.1_amd64.deb

libtinfo.so.5: no version information available (required by sh)​

参考文献：(原创)Ubuntu18+ 解决Verdi使用报错的问题 链接库缺失问题 - Linux

# 安装库
sudo apt install libncurses5
# 备份
sudo cp /tools/synopsys2018/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64/libtinfo.so.5 /tools/synopsys2018/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64/libtinfo.so.5.bak
# 复制
sudo cp /lib/x86_64-linux-gnu/libtinfo.so.5 /tools/synopsys2018/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64/libtinfo.so.5

wsl 遇到的问题

固定mac地址

参考文献：WSL 2 - Static MAC Address or Changing MAC After Booting Without Breaking Internet Connection · Issue #5352 · microsoft/WSL

解决方法：修改文件/etc/wsl.conf​

[boot]
command = ip link add bond0 address f0:2f:74:32:97:38 type bond

固定hostname

[network]
hostname = DESKTOP-UTB5G1J

gvimCouldn't register with accessibility bus: Did not receive a reply​

参考文献：d bus - Getting dbind-WARNING's about registering with the accessibility bus - Unix & Linux Stack Exchange

export NO_AT_BRIDGE=1

可以添加到/etc/environment​，或者~/.bashrc​

备份和导入

参考文献：wsl2子系统的备份和还原 - CharyGao - 博客园

备份到文件

wsl --export Ubuntu-18.04 D:\Ubuntu-18.04-wsl-eda.tar

导入到系统

wsl  --import Ubuntu-18.04 "E:\wsl_data" "E:\仿真环境\Ubuntu-18.04-wsl-eda-lite.tar"

设置默认用户名

ubuntu1804.exe config --default-user fengbh

其他

bashrc 配置

#******************** synopsys ********************
export DVE_HOME=/tools/synopsys2018/vcs/O-2018.09-SP2
export VCS_HOME=/tools/synopsys2018/vcs/O-2018.09-SP2
export VCS_MX_HOME=/tools/synopsys2018/vcs-mx/O-2018.09-SP2
export LD_LIBRARY_PATH=/tools/synopsys2018/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64
export VERDI_HOME=/tools/synopsys2018/verdi/Verdi_O-2018.09-SP2
export SCL_HOME=/tools/synopsys2018/scl/2018.06

#dve
PATH=$PATH:$VCS_HOME/gui/dve/bin
alias dve="dve"

#VCS
PATH=$PATH:$VCS_HOME/bin
alias vcs="vcs"

#VERDI
PATH=$PATH:$VERDI_HOME/bin
alias verdi="verdi"

#scl
PATH=$PATH:$SCL_HOME/linux64/bin
export VCS_ARCH_OVERRIDE=linux

#LICENCE
export LM_LICENSE_FILE=27000@DESKTOP-UTB5G1J
alias lmg="lmgrd -c /tools/synopsys2018/scl/2018.06/admin/license/Synopsys.dat"

#******************** normal ********************
alias e="gvim ~/.bashrc"
alias s="source ~/.bashrc"

测试项目

testbench.sv

`timescale 1ns / 1ns
module testbench;
    reg clk=0, rst_n=1;
    always #5 clk = ~clk;

    reg [7:0] cnt;
    always @(posedge clk or negedge rst_n)
        if(!rst_n) 
            cnt <= 0;
        else 
            cnt <= cnt +1;

    initial begin
		rst_n = 0;
		#10 rst_n =1;
        $display("Hello world!");
        #1000 $finish;
    end
endmodule

Makefile

comp:
	- vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed \
		-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a \
		+vcs+fsdbon -debug_access+all -ntb_opts uvm-1.2 \
		-top testbench -l compile.log -timescale=1ns/1ps\
		testbench.sv

sim:
	- ./simv -l sim.log +fsdbfile+wave.fsdb +fsdb+no_msg+Flush +fsdb+delta +fsdb+sva_sucess +fsdb+glitch=0 +fsdb+sequential

verdi:
	- verdi -sverilog +v2k testbench.sv &

clean:
	- \rm -rf *.log *.fsdb simv.daidir

‍