CSC3050 Project 4: Cache Simulation

CSC3050 Project 4: Cache Simulation

CSC3050 Teaching GroupNovember 20, 2024

1 Introduction Cache is an important component of a CPU system that has a significant impact on computerperformance by reducing memory access times. The focus of this project is to simulate thecache in the RISC-V architecture to give you hands-on experience with the cache systemand its role in improving system performance.

2 OverviewThis project is divided into three main parts:

1. Single-Level Cache Simulation: In this part, you are required to design and implement a cache simulator that enables the single-level cache simulation. Moreoveryouneed to use the single-level cache simulator you implemented to compare the cacheperformance under different cache parameters.

Multi-level Cache Simulation: In this part, based on the single-level cache simulator, you are required to further implement a multi-level cache simulator. You needto examine further how a multi-level cache can improve performance compared to asingle-level cache.

3. Implementation of Pre-fetching: In this section, you are required to implementa critical technique known as pre-fetching. Moreover, you need to compare the cacheperformance with and without pre-fetching3 Single-Level Cache Simulation

• Implementation Requirements: You are required to implement a Cache class fosimulating a single-level cache (The code from [1] is a reference code for your). Thefile structure and description you may use are shown in Table 1.The simulated cache should beable to perform some parameter tuning, such as cachesize, block size, and associativity level. Besides that, you are required to simulate

1file name

Discription

include/Cache.hStatement of the Cache class.src/Cache.cppImplementation of Cache class.src/MainSinCache.cpMain entrance of the single-level cache simulator.src/MainMulCache.cppMain entrance of the multi-level cache simulator.Table 1: File structure and description of single-level and multi-level cache simulation.Parameter Values CTrue or FalseWrite AllocateTrue of False.Table 2: Parameters used in single-level cache simulation.Write Back and Write Allocate policies using the LRU replacement algorithm in yoursaved in a CSV file.

• Performance Evaluation: After the implementation, you are required to evaluatthe cache performance based on your simulator. We will provide you with a test trace(test.trace) to facilitate the performance evaluation. What you can do includes but isnot limited to– Analyzing the trend of Miss Rate with Block Size under different cache sizes– Analyzing the change of Associativity with Miss Rate under different cache sizes– Analyzing the amount of cache misses per thousand instructions under differentcache sizesYouare also free to design scenarios for performance evaluation as you wish. Butplease analyze the performance in at least two different scenarios. You should providegraphical or tabular data and conduct the analysis based on the data mentioned above.The results and analysis should be given in your report.4 Multi-Level Cache Simulation

• Implementation Requirements: You are required to simulate the multi-level cachein this part based on your single-level cache simulator.

• Performance Evaluation: You should conduct the comparison between the singlelevel and multi-level cache system whose parameters are given in Table 3 and Table4, respectively. The cache miss latency is set to 100 CPU cycles. Also, graphical or

2tabular data are required and you should put the comparisons and analysis in yourL32 MB16 ways64 BytesWrite Back20 CPU CycleTable 4: Cache parameters for multi-levelcache.5 Pre-Fetching Implementation Implementation Requirements: Based on the multi-level cache simulation, you arerequired to further add the pre-fetching technique. Specifically, the mechanism is will implement a pre-fetching algorithm capable of detecting fixed-stride memoryaccess patterns; the pseudo-code of the algorithm is summarized in Algorithm 1.Algorithm1 Stride-Based Pre-fetching Algorithm1: initialize: stride = 0, is prefetch = false.2: for Each Memory Access do 3:Calculate the memory access stride (the distance between the current 代写 CSC3050 Project 4: Cache Simulation memory accesif is prefetch = false and there are more than three times with the same stride then 5:is prefetch = true6:prefetch address = current address + stride7:Prefetching(prefetch address8:Performance Evaluation: You are required to compare the performance of a multilevel cache with and without pre-fetching. The setting of the multi-level cache isthesame as that in the previous part. Moreover, the test prefetch.trace is the test trace3specificallyThe results should be included in your report.

6 Submission For this project, you must use C/C++ to implement the cache simulator. If you use otherlanguages, you will get a 0 score. You need to submit the following files:

• src/*: include all source code files
• include/*: include all header files
• CMakelists.txt: the cmake file for your project
• project-report.pdf: a detailed description of your implementation. The specific things

need to be included are as follows– The implementation details of your simulator.– Performance evaluation and analysis mentioned above.Please compress all files into a single zip file and submit it to the BlackBoard. The file nameshould be your student ID, like 221019040.zip.

7 Grading DetailsThe overall score will be calculated as follows:

• Single-level cache simulation code: 20%
• Multi-level cache simulation code: 20%
• Pre-Fetching implementation code: 40%
• Report: 20%For the code, we will check whether your code can run or not. Please make sure that yourcode runs correctly. If the code does not run, it will be directly marked as 0 points.

8 About the reference code To reduce the difficulty and complexity of implementation, we encourage you to refer to

existing code like [1]. This project is also designed based on [1]. However, if you simplysubmit the code from the reference [1] or only do simple tasks like adding comments, weconsider that you haven’t put much effort and your grade will be directly markedaszero.