IP核学习之判断自定义ram与xilinx_sdpram_00reg_64x36IP核的功能是否一致

xilinx_sdpram_00reg_64x36IP核是一个简单的64个地址，每个地址存36位数据且没有输出寄存器的双端口ram，以下是自定义ram的代码，接口与该IP核的接口设定一致：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity sdpram_64x36_test is
    Port (
        clka : in STD_LOGIC;
        clkb : in STD_LOGIC;
        addra : in STD_LOGIC_VECTOR(5 downto 0);
        addrb : in STD_LOGIC_VECTOR(5 downto 0);
        dina : in STD_LOGIC_VECTOR(35 downto 0);
        wea : in STD_LOGIC;
        ena : in STD_LOGIC;
        enb : in STD_LOGIC;
        doutb : out STD_LOGIC_VECTOR(35 downto 0)
    );
end sdpram_64x36_test;

architecture Behavioral of sdpram_64x36_test is
    type ram_type is array (0 to 63) of STD_LOGIC_VECTOR(35 downto 0);
    signal memory : ram_type := (others => (others => '0'));
begin
    -- Port A process for writing data
    PortA: process(clka)
    begin
        if rising_edge(clka) then
            if ena = '1' and wea = '1' then
                memory(to_integer(unsigned(addra))) <= dina;
            end if;
        end if;
    end process PortA;
    
    -- Port B process for reading data
    PortB: process(clkb)
    begin
        if rising_edge(clkb) then
            if enb = '1' then
                doutb <= memory(to_integer(unsigned(addrb)));
            end if;
        end if;
    end process PortB;
    
end Behavioral;

下面是该IP核的介绍信息，该IP核的datasheet链接:https://download.csdn.net/download/u012154529/12102131?spm=1001.2101.3001.6650.1&utm_medium=distribute.pc_relevant.none-task-download-2%7Edefault%7EBlogCommendFromBaidu%7ECtr-1-12102131-blog-129224964.235%5Ev43%5Epc_blog_bottom_relevance_base9&depth_1-utm_source=distribute.pc_relevant.none-task-download-2%7Edefault%7EBlogCommendFromBaidu%7ECtr-1-12102131-blog-129224964.235%5Ev43%5Epc_blog_bottom_relevance_base9&utm_relevant_index=2

以下是testbench的编写：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity sdpram_comparison_tb is
-- 测试平台不需要端口
end sdpram_comparison_tb;

architecture testbench of sdpram_comparison_tb is
    -- 信号声明
    signal clka, clkb : STD_LOGIC := '0';
    signal addra, addrb : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
    signal dina : STD_LOGIC_VECTOR(35 downto 0) := (others => '0');
    signal wea, ena, enb : STD_LOGIC := '0';
    signal doutb_custom, doutb_ip : STD_LOGIC_VECTOR(35 downto 0);

    -- 实例化自定义的RAM
    component sdpram_64x36_test
        Port (
            clka : in STD_LOGIC;
            clkb : in STD_LOGIC;
            addra : in STD_LOGIC_VECTOR(5 downto 0);
            addrb : in STD_LOGIC_VECTOR(5 downto 0);
            dina : in STD_LOGIC_VECTOR(35 downto 0);
            wea : in STD_LOGIC;
            ena : in STD_LOGIC;
            enb : in STD_LOGIC;
            doutb : out STD_LOGIC_VECTOR(35 downto 0)
        );
    end component;

    -- 实例化Xilinx的IP核
    component xilinx_sdpram_00reg_64x36
        Port (
            clka : in STD_LOGIC;
            clkb : in STD_LOGIC;
            addra : in STD_LOGIC_VECTOR(5 downto 0);
            addrb : in STD_LOGIC_VECTOR(5 downto 0);
            dina : in STD_LOGIC_VECTOR(35 downto 0);
            wea : in STD_LOGIC;
            ena : in STD_LOGIC;
            enb : in STD_LOGIC;
            doutb : out STD_LOGIC_VECTOR(35 downto 0)
        );
    end component;

begin
    -- 实例化自定义的RAM
    custom_ram: sdpram_64x36_test 
        port map (
        clka => clka,
        clkb => clkb,
        addra => addra,
        addrb => addrb,
        dina => dina,
        wea => wea,
        ena => ena,
        enb => enb,
        doutb => doutb_custom
    );

    -- 实例化Xilinx的IP核
    ip_ram: xilinx_sdpram_00reg_64x36IP 
        port map (
        clka => clka,
        clkb => clkb,
        addra => addra,
        addrb => addrb,
        dina => dina,
        wea => wea,
        ena => ena,
        enb => enb,
        doutb => doutb_ip
    );

    -- 时钟生成过程
    clock: process
    begin
        while true loop
            clka <= '1';
            clkb <= '1';
            wait for 10 ns;
            clka <= '0';
            clkb <= '0';
            wait for 10 ns;
        end loop;
    end process;

    -- 测试过程
    test: process
    begin
        -- 初始化
        addra <= (others => '0');
        addrb <= (others => '0');
        dina <= (others => '0');
        wea <= '0';
        ena <= '0';
        enb <= '0';
        wait for 40 ns;

        -- 使能写操作
        ena <= '1';
        wea <= '1';
        for i in 0 to 63 loop
            addra <= std_logic_vector(to_unsigned(i, addra'length));
            dina <= std_logic_vector(to_unsigned(i, dina'length));
            wait for 20 ns;
        end loop;
        wea <= '0'; -- 禁用写使能
        ena <= '0'; -- 禁用端口A

        -- 使能读操作
        enb <= '1';
        for i in 0 to 63 loop
            addrb <= std_logic_vector(to_unsigned(i, addrb'length));
            wait for 20 ns;
            -- 检查输出
            assert doutb_custom = doutb_ip
            report "测试失败：自定义RAM与IP核的读出数据不一致"
            severity error;
        end loop;

        -- 测试完成
        wait;
    end process;
end testbench;

测试结果：与该IP核功能一致

后续的功能验证报告不再详细叙述

补：功能验证（测试代码不再详细叙述）