示例详细信息：
设备： xcvu9p-flga2104-2-e
问题：尽管使用 GCIO 引脚作为时钟，但该工具仍返回 I/O Clock Placer 错误
错误：
<span style="background-color:#f3f3f3"><span style="color:#333333"><code>ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <input_buffer>/O] >
Clock Rule: rule_gclkio_bufg
Status: FAILED
Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG
<input_buffer>/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y338 (in SLR 1)
The loads are distributed to 3 user pblock constraints. In addition, there are 4 loads not in user pblock constraints.
Displaying first 4 loads not in user pblock constraint:
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y161 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y160 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y162 (in SLR 1)
Displaying the first 10 loads for pblock constraint 1
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y167 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y166 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y156 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y165 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y157 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y158 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y164 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y163 (in SLR 1)
Displaying the first 1 loads for pblock constraint 2
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y143 (in SLR 1)
Displaying the first 1 loads for pblock constraint 3
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y119 (in SLR 0)
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y161 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y160 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y162 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y163 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y164 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y158 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y157 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y165 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y156 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y166 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y167 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y143 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y119 (in SLR 0)
Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same bank of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <input_buffer>/O] >
Clock Rule: rule_gclkio_bufg
Status: FAILED
Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG
<input_buffer>/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y338 (in SLR 1)
The loads are distributed to 3 user pblock constraints. In addition, there are 4 loads not in user pblock constraints.
Displaying first 4 loads not in user pblock constraint:
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y224 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y221 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y218 (in SLR 1)
Displaying the first 10 loads for pblock constraint 1
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y153 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y152 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y151 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y144 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y150 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y149 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y146 (in SLR 1)
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y145 (in SLR 1)
Displaying the first 1 loads for pblock constraint 2
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y121 (in SLR 1)
Displaying the first 1 loads for pblock constraint 3
<some bufg> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y97 (in SLR 0)
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y224 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y221 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y218 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y159 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y145 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y146 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y149 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y150 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y144 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y151 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y152 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y153 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y154 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y155 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y121 (in SLR 1)
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
<some bufg> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y97 (in SLR 0)
Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same bank of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
</code></span></span>这里我们有两个错误与 CLOCK_DEDICATED_ROUTE 约束中提到的同一网络相关。
使用此网络名称，当我们生成网络原理图时，我们可以获取分配给封装引脚 R34 的输入时钟端口。这可以在时钟端口的属性窗口中找到。
然后，示意图显示 17 个 BUFG 由同一端口驱动，其中一些 BUFG 已分配给 PBLOCK。
在放置端口步骤之后，当我们标记这些 BUFG 时，我们可以在设备视图中看到，除了两个之外，所有 BUFG 都放置在同一个时钟区域中，从而遵守规则表中的规则 1。
在检查异常 BUFG 的约束时，我们发现用户 PBLOCK 强制将这两个放置在 I/O 组旁边的时钟区域之外，因此出现 CDR 错误。
用户 PBLOCK 正在将一个缓冲区分配给下面的时钟区域，并将另一个缓冲区分配给下面的第二个时钟区域。 
这种放置与规则 1 冲突，因此仅从 PBLOCK 中移除 BUFG 是正确的解决方案。没有必要将 BUFG 放入 PBLOCK 中，因为这会造成不必要的限制。
在后续运行中，将 BUFG 从 PBLOCK 中移除后，工具在放置过程中不会出错。
检查后发现，所有 BUFG 都被放置在同一个时钟区域，因此遵循规则 1。
标签：BUFGCE,示例,UltraScale,Rule,clockplacer,placed,SLR,xilinx,provisionally From： https://blog.csdn.net/sqqwm/article/details/141366395