Error-[XMRE] Cross-module reference resolution error
/opt/xilinx/Vivado/2019.2/data/verilog/src/unisims/OSERDESE2.v, 134
Error found while trying to resolve cross-module reference.
token 'glbl'. Originating module 'OSERDESE2'.
Source info: assign GSR = glbl.GSR;
Instance stack trace:
OSERDESE2#("DDR", "DDR", 10, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, "MASTER", 1'b0, 1'b0,
"FALSE", "FALSE", 4) ./../../design/rtl/serializer_10_to_1.v, 53
serializer_10_to_1#(10) ../../verify/tb/tb_top.sv, 39
tb_top ../../verify/tb/tb_top.sv, 3
在 Xilinx 提供的库中，glbl 是一个全局信号模块，通常用于包含全局复位（GSR）和全局时钟启用（GTS）等信号。在仿真环境中，glbl 模块用于模拟全局信号对设计的影响。然而，当在使用仿真工具（如 Verdi）进行调试时，如果没有正确包含 glbl 模块，可能会导致解析错误。
我们首先检查我们的Makefile文件
在vlogan命令中需要添加glbl的路径，如果没有glbl.v的话我们需要创建一个glbl.v
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
再在vlogan里面添加glbl.v，将glbl.v编译到xil_defaultlib库中
compile:
vlogan \
+v2k \
-full64 \
-work xil_defaultlib \
"/opt/vivado/glbl.v" \
然后我们需要再vcs命令添加glbl
elaborate:
vcs \
-full64 \
-cpp g++-4.8 -cc gcc-4.8 -LDFLAGS -Wl,--no-as-needed \
-Mdir=./vcs_lib/xil_defaultlib \
-sverilog \
-debug_acc+all -debug_region+cell+encrypt \
$(verdi_opts) \
xil_defaultlib.${tc} xil_defaultlib.glbl\
-o simv \
2>&1 | tee -a vlogan.log