标签：缓存 Name fpga buffer img FIFO input data Revision
FPGA实现
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/08/18 13:47:22
// Design Name:
// Module Name: line_buffer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module line_buffer(
input clk ,
input rst ,
input [ 10: 0] img_width ,
input valid_i ,
input [ 23: 0] img_data_i ,
output valid_o ,
output [ 23: 0] img_data_o
);
reg [ 10: 0] wr_data_cnt ;
wire rd_en
标签：缓存,
Name,
fpga,
buffer,
img,
FIFO,
input,
data,
Revision
From： https://blog.csdn.net/weixin_62953178/article/details/141300405