FPGA加扰与仿真

对加扰仿真，输出结果符合预期

仿真代码如下

module scrambler_64bit(
    input wire clk,
    input wire rst,
    input wire [63:0] data_in,
    output reg [63:0] data_out
);

reg [63:0] state;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        state <= 64'hFFFFFFFFFFFFFFFF; 
    end else begin
        state <= state + 64'hAAAAAAAAAAAAAAAA; // 64位加法扰乱器
    end
end

assign data_out = data_in ^ state; // 异或

endmodule

module descrambler_64bit(
    input wire clk,
    input wire rst,
    input wire [63:0] data_in,
    output reg [63:0] data_out
);

reg [63:0] state;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        state <= 64'hFFFFFFFFFFFFFFFF; // 初始化，需与加扰器一致
    end else begin
        state <= state + 64'hAAAAAAAAAAAAAAAA; // 解扰器状态更新，需与加扰器保持同步
    end
end

assign data_out = data_in ^ state; // 异或恢复原始数据

endmodule

module tb_scrambler_descrambler_64bit();

reg clk;
reg rst;
reg [63:0] data_in;
wire [63:0] scrambled_data;
wire [63:0] descrambled_data;

scrambler_64bit scrambler_inst (
    .clk(clk),
    .rst(rst),
    .data_in(data_in),
    .data_out(scrambled_data)
);

descrambler_64bit descrambler_inst (
    .clk(clk),
    .rst(rst),
    .data_in(scrambled_data),
    .data_out(descrambled_data)
);

// Clock generation
always #5 clk = ~clk;

initial begin
    clk = 0;
    rst = 1;
    data_in = 64'h12340000ABCD0000; 
    #10 rst = 0; 
    #100;
    $display("Input Data: %h", data_in);
    $display("Scrambled Data: %h", scrambled_data);
    $display("Descrambled Data: %h", descrambled_data);
    // $finish;
end

endmodule