一组给定的语句可以使用构造执行N次。repeat
Syntax
repeat (<number>)
// Single Statement
repeat (<number>) begin
// Multiple Statements
end
Example #1
module tb;
initial begin
repeat (5) begin
$display ("Repeat this statement");
end
end
endmodule
模拟日志
ncsim> run
Repeat this statement
Repeat this statement
Repeat this statement
Repeat this statement
Repeat this statement
ncsim: *W,RNQUIE: Simulaltion is complete.
循环也可以使用循环实现,但更冗长。如果不需要在循环中引用变量i
,则循环会更合适。repeat
for repeat
for (int i = 0; i < number; i++) begin
// Code
end
在下面显示的代码中,我们有一个循环来等待给定数量的时钟周期。repeat
module tb;
bit clk;
always #10 clk = ~clk;
initial begin
bit [2:0] num = $random;
$display ("[%0t] Repeat loop is going to start with num = %0d", $time, num);
repeat (num) @(posedge clk);
$display ("[%0t] Repeat loop has finished", $time);
$finish;
end
endmodule
在此示例中,时钟周期为20ns,时钟的第一个位置发生在10ns。接下来的3个时钟位置发生在30ns、50ns和70ns之间,之后初始块结束。因此,此循环成功等待,直到4个时钟结束。repeat
模拟日志
ncsim> run
[0] Repeat loop is going to start with num = 4
[70] Repeat loop has finished
ncsim: *W,RNQUIE: Simulaltion is complete.
标签:begin,Repeat,num,--,3.5,SystemVerilog,statement,end,repeat
From: https://www.cnblogs.com/sys-123456/p/18173783