SystemVerilog while and do-while loop
两者都是循环构造，只要给定条件为真，就会执行给定的语句集。while do while
循环首先检查条件是否为true，如果条件为true，则执行语句。如果条件被证明是假的，则循环就在哪里结束。while
循环首先执行一次语句，然后检查条件是否为true。如果条件为true，则执行该语句集，直到条件变为false。如果条件为false，则循环将在此处结束。do while
因此，两者之间的区别在于，循环至少执行一次语句集。do while
Syntax
while (<condition>) begin
// Multiple statements
end
do begin
// Multiple statements
end while (<condition>);
Example #1 - while loop
module tb;
initial begin
int cnt = 0;
while (cnt < 5) begin
$display("cnt = %0d", cnt);
cnt++;
end
end
endmodule
模拟日志
ncsim> run
cnt = 0
cnt = 1
cnt = 2
cnt = 3
cnt = 4
ncsim: *W,RNQUIE: Simulation is complete.
Example #2
module tb;
initial begin
int cnt;
while (cnt != 0) begin
$display("cnt = %0d", cnt);
cnt++;
end
end
endmodule
模拟日志
ncsim> run
ncsim: *W,RNQUIE: Simulation is complete.
Example #3 - do while loop
module tb;
initial begin
int cnt = 0;
do begin
$display("cnt = %0d", cnt);
cnt++;
end while (cnt < 5);
end
endmodule
模拟日志
ncsim> run
cnt = 0
cnt = 1
cnt = 2
cnt = 3
cnt = 4
ncsim: *W,RNQUIE: Simulation is complete.
Example #4 - do while loop
module begin
initial begin
int cnt = 0;
do begin
$display("cnt = %0d", cnt);
cnt++;
end while (cnt == 0);
end
end
模拟日志
ncsim> run
cnt = 0
ncsim: *W,RNQUIE: Simulation is complete.