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SystemVerilog -- 2.0 Data Types ~ Introduction

时间:2024-04-13 20:55:22浏览次数:23  
标签:comment -- 0x0 myArray Introduction int myFIFO display SystemVerilog

SystemVerilog Data Types

SystemVerilog 是 Verilog 的扩展,也用作 HDL。Verilog 具有和数据类型来描述硬件行为。由于硬件验证可能变的更加复杂和苛刻,Verilog 中的数据类型不足以开发高效的测试平台和测试用例。因此,SystemVerilog 通过添加更多类似 C 的数据类型和扩展 Verilog,以获得更好的封装和紧凑性。reg wire

下图是 SystemVerilog 中可用的主要基本数据类型的完整列表。

How to write comments ?

// This is a one-line comment

/* This is a multiple line comment.
   Since this line is within the block comment symbols, it is a comment.
*/

/* Another multiple line comment.
   A nested one-line comment inside a block comment is fine.
   but a block comment cannot be nested in another block comment.
*/

Values SystemVerilog variables can hold

以下是variable or net可以保持的四种状态。

0 Logic state 0 - variable/net is at volts
1 Logic state 1 - variable/net is at some value > 0.7 volts
x or X Logic state X - variable/net has either 0/1 - we just don't know
z or Z Logic state Z - net has high impedence - maybe the wire is not connected and is floating

How to write floating point and exponential numbers ?

设置定点格式。例如 2.8 或指数格式(例如 7.2e6)

module tb;
  real pi;  // Declared to be of type real
  real freq;

  initial begin
    pi   = 3.14;
    freq = 1e6;

    $display("Value of pi = %f", pi);
    $display("Value of pi = %0.3f", pi);
    $display("Value of freq = %0d", freq);
  end
endmodule

模拟日志

ncsim> run
Value of pi = 3.140000
Value of pi = 3.140
Value of freq = 1000000.000000
ncsim: *W,RNQUTE: Simulation is complete.

What are SystemVerilog strings ?

//Strings can be split into multiple lines (for visual appeal) by the using "" character
//This does not split the string into multiple lines in the output.
//Result: New York is an awesome place. So energetic and vibrant.
$display ("New York is an awesome place. So energetic and vibrant.");

// Strings can be split to be displayed in multiple lines using " "
/* Result:
          New York is an awesome place.
          So energetic and vibrant.
*/
$display (New York is an awesome place.
          So energetic and vibrant.);

// To store a string literal in an integral type, each character will require 8 bits
byte      myLetter  = "D";
bit [7:0] myNewLine = "";

//"Hello World" has 11 characters and each character requires 8-bits
bit [8*17:1] myMessage  = "Hello World";
string       myMessage2 = "Hello World"; // use "string" data type

What are structures ?

A 表示存储在一起并通过结构变量引用的数据烈性的集合。structure

//Create a structure to store "int" and "real" variables
//A name is given to the structure and declared to be a data type so
//that this name "" can be used to create structure variables 
typedef struct {
    int   coins;
    real dollars;
} s_money;

// Create a structure variable of type s_money
s_money wallet;

wallet = '{5, 19.75};                   // Assign direct values to a structure variable
wallet = '{coins:5, dollars:19.75};     // Assign values using member names
wallet = '{default:0};                  // Assign all elements of structure to 0
wallet = s_money'{int:1, dollars:2};    // Assign default values to all members of that type

// Create a structure that can hold 3 variables and initialize them with 1
struct {
    int A, B, C;
} ABC = {3{1}};  // A = B = C = 1

// Assigning an array of structures
s_money purse [1:0] = '{'{2,4.25}, '{7,1.5}};

What are fixed size arrays ?

数组是一个变量,用于在连续位置存储不同的值。

module tb;
// The following two representations of fixed arrays are the same
// myFIFO and urFIFO have 8 locations where each location can hold an integer value
// 0,1 | 0,2 | 0,3 | ... | 0,7
int myFIFO [0:7];
int urFIFO [8];

// Multi-dimentional arrays
// 0,0 | 0,1 | 0,2 | 
int myArray [2][3];

initial begin
    myFIFO[5]     = 32'hface_cafe;
    myArray[1][1] = 7;

    // Iterate through each element in the array
    foreach (myFIFO[i])
      $display ("myFIFO[%0d] = 0x%0h", i, myFIFO[i]);

    // Iterate through each element in the multidimensional array
    foreach (myArray[i])
      foreach (myArray[i][j])
        $display ("myArray[%0d][%0d] = %0d", i, j, myArray[i][j]);
end
endmodule

模拟日志

ncsim> run
myFIFO [0] = 0x0
myFIFO [1] = 0x0
myFIFO [2] = 0x0
myFIFO [3] = 0x0
myFIFO [4] = 0x0
myFIFO [5] = 0x0
myFIFO [6] = 0x0
myFIFO [7] = 0x0
myArray[0][0] = 0
myArray[0][1] = 0
myArray[0][2] = 0
myArray[1][0] = 0
myArray[1][1] = 0
myArray[1][2] = 0
ncsim: *W,RNQUTE: Simulation is complete.

void data-type

data-type 表示不存在的数据,可以指定为函数和任务的返回类型,以指示无返回值。void

function void display ();
    $display ("Am not going to return any value");
endfunction

task void display ();
    #10 $display ("Me neither");
endtask

Conversion of real to int

实数将通过将实数四舍五入到最接近的整数而不是截断它来转换为整数。如果小数部分正好是 0.5,它将从零开始四舍五入。可以使用强制转换或使用系统任务来指定显示转换。直接将实值分配给整数类型也将舍入而不是截断。

// casting will perform rounding
int'(2.0*3.0)
shortint'({8'hab, 8'hef})

// Using system tasks will truncate
integer $rtoi (real_val)
integer $rtoi (int_val)

标签:comment,--,0x0,myArray,Introduction,int,myFIFO,display,SystemVerilog
From: https://www.cnblogs.com/sys-123456/p/18132754

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