模板-V1
模型功能
- 输入视频总线
- 输出视频总线
- 将RGB24数据转化为灰度数据
模型框图
控制模型
实现步骤
源码编写
- 未经仿真的原始代码
`timescale 1ns / 1ps
/*
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/04/05 13:24:26
// Design Name:
// Module Name: video_gray_cacu
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// FUNC1: output gray
//////////////////////////////////////////////////////////////////////////////////
module video_gray_cacu #(
//mode
parameter MD_SIM_ABLE = 0,
//number
//width
parameter WD_DATA = 24,
parameter WD_BYTE = 8,
parameter WD_ERR_INFO = 4
)(
//system signals
input i_sys_clk ,
input i_sys_resetn,
//video src
input s_video_src_fsync,
input s_video_src_vsync,
input s_video_src_hsync,
input s_video_src_psync,
input [WD_DATA-1:0] s_video_src_vdata,
//video dst
output m_video_dst_fsync,
output m_video_dst_vsync,
output m_video_dst_hsync,
output m_video_dst_psync,
output [WD_DATA-1:0] m_video_dst_vdata,
//error info feedback
output [WD_ERR_INFO-1:0] m_err_video_info1
);
//========================================================
//function to math and logic
//========================================================
//localparam to converation and calculate
localparam NB_CACU_STEP = 2;
//========================================================
//register and wire to time sequence and combine
// ----------------------------------------------------------
// FUNC1: output gray
reg [NB_CACU_STEP-1:0] r_video_dst_fsync_dn = 0;
reg [NB_CACU_STEP-1:0] r_video_dst_vsync_dn = 0;
reg [NB_CACU_STEP-1:0] r_video_dst_hsync_dn = 0;
reg [NB_CACU_STEP-1:0] r_video_dst_psync_dn = 0;
reg [WD_DATA-1:0] r_video_dst_vdata = 0;
assign m_video_dst_fsync = r_video_dst_fsync_dn[NB_CACU_STEP-1];
assign m_video_dst_vsync = r_video_dst_vsync_dn[NB_CACU_STEP-1];
assign m_video_dst_hsync = r_video_dst_hsync_dn[NB_CACU_STEP-1];
assign m_video_dst_psync = r_video_dst_psync_dn[NB_CACU_STEP-1];
assign m_video_dst_vdata = r_video_dst_vdata;
//cacu-1
reg [WD_DATA+1-1:0] r_video_R_add_B;
reg [WD_DATA+1-1:0] r_video_G_mul_2;
//cacu-2
wire [WD_DATA+2-1:0] w_video_R_add_B_add_2G;
//========================================================
//always and assign to drive logic and connect
// ----------------------------------------------------------
// FUNC1: output gray
always@(posedge i_sys_clk)
begin
if(!i_sys_resetn) //system reset
begin
r_video_R_add_B <= 1'b0; //
r_video_G_mul_2 <= 1'b0;
end
else if(1) //
begin
r_video_R_add_B <= s_video_src_vdata[WD_BYTE*1-1:WD_BYTE*0] //R
+ s_video_src_vdata[WD_BYTE*3-1:WD_BYTE*2]; //B //
r_video_G_mul_2 <= {s_video_src_vdata[WD_BYTE*2-1:WD_BYTE*1],1'b0};
end
end
assign w_video_R_add_B_add_2G = r_video_R_add_B + r_video_G_mul_2;
always@(posedge i_sys_clk)
begin
if(!i_sys_resetn) //system reset
begin
r_video_dst_fsync_dn <= 1'b0;
r_video_dst_vsync_dn <= 1'b0;
r_video_dst_hsync_dn <= 1'b0;
r_video_dst_psync_dn <= 1'b0;
r_video_dst_vdata <= 1'b0;//
end
else if(1) //
begin
r_video_dst_fsync_dn <= {r_video_dst_fsync_dn[NB_CACU_STEP-2:0],s_video_src_fsync};
r_video_dst_vsync_dn <= {r_video_dst_vsync_dn[NB_CACU_STEP-2:0],s_video_src_vsync};
r_video_dst_hsync_dn <= {r_video_dst_hsync_dn[NB_CACU_STEP-2:0],s_video_src_hsync};
r_video_dst_psync_dn <= {r_video_dst_psync_dn[NB_CACU_STEP-2:0],s_video_src_psync};
r_video_dst_vdata <={(3){w_video_R_add_B_add_2G[WD_BYTE+2-1:2]}};// //
end
end
//========================================================
//module and task to build part of system
//========================================================
//expand and plug-in part with version
//========================================================
//ila and vio to debug and monitor
endmodule
/* end verilog
*/
video总线描述
- 使用自定义video总线，包括帧同步、垂直同步、水平同步、像素点同步和数据五个信号
- 总线的时序图如下：
获取测试端口
| 测试端口 | 测试目标 |
|---|---|
| 复位测试 | 仿真无非0和1的值进入初始化即可 |
| video输入 | 总线的数据同步格式正常； |
| video输出 | 总线的数据和输入的理论计算结果一致 |
| 报错信息 | 无 |
最终效果
封装模型
调用接口
调用参数配置
- 只是演示仿真仿真系统如何搭建，所以DUT可以比较简单，只需要引入基本的总线概念即可