FPGA入门笔记008——数码管动态扫描设计与验证

​ 增加一个模块：HC595_Driver.v，将HEX8.v输出的sel和seg信号（Data）转换为连接74HC595芯片上的LATCH信号（ST_CP）、DATA信号（DS）和CLK（SH_CP）信号。3.3V供电情况下，取SH_CP时钟频率为12.5MHz（80ns），则可以让其每40ns翻转一次。也就是每2个系统时钟周期（CLK：20ns）翻转一次。代码如下：

module HC595_Driver(
    Clk,
    Rst_n,
    Data,
    S_EN,    //移位使能信号，控制是否输出数据
    SH_CP,   //Shift_Clock
    ST_CP,   //LATCH_Clock
    DS
);
    input Clk;
    input Rst_n;
    input [15:0]Data;
    input S_EN;

    output reg SH_CP;
    output reg ST_CP;
    output reg DS;

//使能信号
    reg [15:0]r_data;
    always@(posedge Clk)
    if(S_EN)
        r_data <= Data;

//分频器
    parameter CNT_MAX = 2;  //12.5MHz，CNT_MAX = 2（每两个时钟周期翻转一次）；若是6.25MHz，则CNT_MAX = 4（每四个时钟周期翻转一次）。
	
    //计数器
    reg [7:0]divider_cnt;   

    always@(posedge Clk or negedge Rst_n)
    if(!Rst_n)
        divider_cnt <= 0;
    else if(divider_cnt == CNT_MAX - 1'b1)   //每2个时钟周期翻转一次：0、1
        divider_cnt <= 0;
    else
        divider_cnt <= divider_cnt + 1'b1;
	
    //sck_plus脉冲
    wire sck_plus;
    assign sck_plus = (divider_cnt == CNT_MAX - 1'b1);

	//边沿计数器，计数到32
    reg [5:0]SHCP_EDGE_CNT;

    always@(posedge Clk or negedge Rst_n)
    if(!Rst_n)
        SHCP_EDGE_CNT <= 0;
    else if(sck_plus)begin
        if(SHCP_EDGE_CNT == 32)
            SHCP_EDGE_CNT <= 0;
        else
            SHCP_EDGE_CNT <= SHCP_EDGE_CNT + 1'b1;
    end
    else
        SHCP_EDGE_CNT <= SHCP_EDGE_CNT;

//产生ST_CP、SH_CP、DS信号
    always@(posedge Clk or negedge Rst_n)
    if(!Rst_n)begin
        ST_CP <= 1'b0;
        DS <= 1'b0;
        SH_CP <= 1'b0;
    end
    else begin
        case(SHCP_EDGE_CNT)
            0:begin SH_CP <= 0; ST_CP <= 1'd0; DS <= r_data[15];end
            1:begin SH_CP <= 1;end
            2:begin SH_CP <= 0; DS <= r_data[14];end
            3:begin SH_CP <= 1;end

            4:begin SH_CP <= 0; DS <= r_data[13];end
            5:begin SH_CP <= 1;end
            6:begin SH_CP <= 0; DS <= r_data[12];end
            7:begin SH_CP <= 1;end

            8:begin SH_CP <= 0; DS <= r_data[11];end
            9:begin SH_CP <= 1;end
            10:begin SH_CP <= 0; DS <= r_data[10];end
            11:begin SH_CP <= 1;end

            12:begin SH_CP <= 0; DS <= r_data[9];end
            13:begin SH_CP <= 1;end
            14:begin SH_CP <= 0; DS <= r_data[8];end
            15:begin SH_CP <= 1;end

            16:begin SH_CP <= 0; DS <= r_data[7];end
            17:begin SH_CP <= 1;end
            18:begin SH_CP <= 0; DS <= r_data[6];end
            19:begin SH_CP <= 1;end

            20:begin SH_CP <= 0; DS <= r_data[5];end
            21:begin SH_CP <= 1;end
            22:begin SH_CP <= 0; DS <= r_data[4];end
            23:begin SH_CP <= 1;end

            24:begin SH_CP <= 0; DS <= r_data[3];end
            25:begin SH_CP <= 1;end
            26:begin SH_CP <= 0; DS <= r_data[2];end
            27:begin SH_CP <= 1;end

            28:begin SH_CP <= 0; DS <= r_data[1];end
            29:begin SH_CP <= 1;end
            30:begin SH_CP <= 0; DS <= r_data[0];end
            31:begin SH_CP <= 1;end

            32:ST_CP <= 1'd1;
            default:
                begin
                    ST_CP <= 1'b0;
                    DS <= 1'b0;
                    SH_CP <= 1'd0;
                end
        endcase
    end

endmodule

8、串行移位寄存器驱动仿真

`timescale 1ns/1ns
`define clk_period 20

module HC595_Driver_tb;

    reg Clk;
    reg Rst_n;
    reg [15:0]Data;
    reg S_EN;

    wire SH_CP;
    wire ST_CP;
    wire DS;

    HC595_Driver HC595_Driver(
        .Clk(Clk),
        .Rst_n(Rst_n),
        .Data(Data),
        .S_EN(S_EN),    //移位使能信号，控制是否输出数据
        .SH_CP(SH_CP),   //Shift_Clock
        .ST_CP(ST_CP),   //LATCH_Clock
        .DS(DS)
    );

    initial Clk = 1;
    always#(`clk_period/2) Clk = ~Clk;

    initial begin
        Rst_n = 0;
        #201
        Rst_n = 1;
        #200
        S_EN = 0;
        Data = 16'h1234;
        #201;
        S_EN = 1;
        #2000;
        S_EN = 0;
        #200000;
        Data = 16'h8765;
        S_EN = 1;
        #2000;
        S_EN = 0;
        #2000;
        $stop;
    end

endmodule

9、将串行移位寄存器驱动加入到HEX_top.v中

module HEX8_top(
    Clk,
    Rst_n,
    SH_CP,
    ST_CP,
    DS
);
    input Clk;  //50M
    input Rst_n;

    output SH_CP;
    output ST_CP;
    output DS;

    wire [7:0]sel;    //数码管位选（选择当前要显示的数码管）
    wire [6:0]seg;    //数码管段选（当前要显示的内容）

    wire[31:0]disp_data;

//ISSP模块
    hex8_data hex8_data(
        .probe(),
        .source(disp_data)
    );

//数码管驱动
    HEX8 HEX8(
        .Clk(Clk),
        .Rst_n(Rst_n),
        .En(1),
        .disp_data(disp_data),
        .sel(sel),
        .seg(seg)
    );

//74HC595驱动模块
    HC595_Driver(
        .Clk(Clk),
        .Rst_n(Rst_n),
        .Data({1'd0,seg,sel}),
        .S_EN(1),    //移位使能信号，控制是否输出数据
        .SH_CP(SH_CP),   //Shift_Clock
        .ST_CP(ST_CP),   //LATCH_Clock
        .DS(DS)
    );

endmodule