sequencer使用
user sequencer类的创建
class gpio_sequencer extends uvm_sequencer #(gpio_transfer);
`uvm_component_utils(gpio_sequencer)
function new (string name,uvm_component parent);
super,new(name,parent);
endfunction
endclass
virtual sequencer的使用
// 创建virtual sequencer
class virtual_sequencer extends uvm_sequencer;
`uvm_component_utils(virtual_sequencer); // 注册
// 三个sequencer的句柄
gpio_sequencer p_gpio_sqr;
uart_sequencer p_uart_1_sqr;
uart_sequencer p_uart_2_sqr;
function new(stirng name,uvm_component parent);
super.new(name,parent);
endfunction
endclass
class base_test extends uvm_test;
// 不同的协议,创建不同的transaction对象
// 使用不同的sequence产生数据
// 使用不同sequencer发送数据
gpio_environment gpio_env;
uart_environment uart_1_env;
uart_environment uart_2_env;
virtual_sequencer v_sqr;
reg_model rn;
my_adapter reg_sqr_adapter;
my_scoreboard scb;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
extern virtual function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual function void report_phase(uvm_phase phase);
`uvm_component_utils(base_test);
endclass
function void base_test::build_phase(uvm_phase phase);
super.build_phase(phase);
// 创建对象
gpio_env = gpio_environment::type_id::create("gpio_env",this);
uart_1_env = uart_environment::type_id::create("uart_1_env",this);
uart_2_env = uart_environment::type_id::create("uart_2_env",this);
v_sqr = my_vsqr::type_id::create("v_sqr",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
v_sqr.p_gpio_sqr = gpio_env.agt.sqr;
v_sqr.p_uart_1_sqr = uart_1_env.agt.sqr;
v_sqr.p_uart_2_sqr = uart_2_env_agt.sqr;
endfunction
uvm_exercise1
1.添加uvm库到验证环境
2.仿真调用case0
3.打印uvm拓扑结构
import uvm_pkg::*
`include "uvm_macros.svh"
program automatic test;
initial begin
run_test();
end
endprogram
program automatic test;
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_test extends uvm_test;
string name;
`uvm_component_utils(my_test); // 注册类
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual function build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("build_test","Hello uvm",UVM_MEDIUM);
end function
virtual task run_phase(uvm_phase phase);
`uvm_info("build_test","Hello uvm",UVM_MEDIUM);
endtask;
endclass
initial begin
run_test();
end
endprogram
打印testbench的结构
test
program automatic test;
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_test extends uvm_test;
string name;
`uvm_component_utils(my_test); // 注册类
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual function build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("build_test","Hello uvm",UVM_MEDIUM);
end function
virtual task run_phase(uvm_phase phase);
`uvm_info("build_test","Hello uvm",UVM_MEDIUM);
endtask;
endclass
initial begin
run_test();
end
endprogram
- 在program定义一个test类,就是testcase对应的类,一个testcase对应一个类,可以定义一个test_base类,将其包含进来
- 在initial begin中使用run_test()启动testbench
test_base
`ifndef TEST_BASE__SV
`define TEST_BASE__SV
// test中要例化env,所以将env.sv文件包含在test_base中
`include "router_env.sv"
class test_base extends uvm_test;
// 注册组件
`uvm_component_utils(test_base);
// 创建env
router_env env;
// 构造函数
function new(string name,uvn_component parent);
super.new(name,parent);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
endfunction
// phase函数
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
env = router_env::type_id::create("env",this);
endfunction
virtual function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation(phase);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
// 打印uvm tb结构信息
uvm_top.print_topology();
// 打印factory当中registry相关的信息
factory.print();
endfunction
endclass
test
program automatic test;
import uvm_pkgs::*;
`include "uvm_maros.svh"
`include "test_base.sv"
initial begin
run_test();
end
endprogram
router_env
- env环境当中例化agent,scoreboard等
`include "input_agent.sv"
class router_env extends uvm_env;
input_agent i_agent;
`uvm_component_utils(router_env);
function new(string name,uvm_component parent);
super.new(name,parent);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
// 通过工厂创建对象
i_agent = input_agent::type_id::create("i_agent",this);
// 设置input squencer执行packet squence作为默认的sequence
uvm_config_db #(uvm_object_wrapper)::set(this,"i_agent.seqr.main_phase","default_sequence",packet_sequence::get_type());
endfunction
endclass
input agent
- agent当中会例化driver,squenecer,monitor
`include "packet_squence.sv"
`include "driver.sv"
`include "monitor.sv"
// 这里直接使用uvm_sequencer做为sequencer
// 实际应该写一个sequencer继承uvm_sequencer
typedef uvm_sequencer #(packet) packet_sequencer;
class input agent extends uvm_agent;
packet_sequencer seqr;
driver drv;
`uvm_component_utils(input_agent)
function new(string name,uvm_component parent);
super.new(name,parent);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
endfunction
virtual function void build_phase(uvm_phase phase) ;
super.build_function(phase);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
seqr = packet_squencer::type_id::create("seqr",this);
drv = driver::type_id::create("drv",this);
endfunction
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info("TRACE",$sformat("%m"),UVM_HIGH);
// 连接sequencer和driver
drv.seq_item_port.connect(seqr.seq_item_export);
endfunction
endclass
driver
class driver extends uvm_driver;
`uvm_component_utils(driver);
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual task run_phase(uvm_phase phase);
// 获取数据发送数据
forever begin
seq_item_port.get_next_item(req);
req.print();
seq_item_port.item_done();
end
endtask
endclass
packet_sequence
class packet_sequence extends uvm_sequence #(packet);
`uvm_object_utils(packet_sequence)
function new(string name);
super.new(name);
endfunction
// 设置默认squence的时候,会自动调用body()
virtual task body();
if(starting phase != null)
starting_phase.raise_objection(this);
repeat(10) begin
`uvm_do(req);
end
if(starting_phase !=null);
starting_phase.drop_objection(this);
endtask
endclass