【代码更新】时序——数字信号处理

 捕获数字信号整体代码如下：

  1 //
  2 //
  3 //`define real_data_source
  4 
  5 //`ifdef    real_data_source
  6 //
  7 //5438400 一帧DCK
  8 //320*15= 4800 象元数据
  9 //323* 15 = 4845 象元数据 + 测试字
 10 //4845 *1024 = 4961280 一帧，1024行
 11 //5438400 – 4961280 = 477120 DCK，除了象元数据外的DCK
 12 //477120 / 1023 = 466 DCK 行间隔
 13 module Digital_capture (
 14 //
 15 input wire  clk_160,//160MHZ
 16 input wire ddr_clk,
 17 //rst
 18 //output reg rst_n,
 19 output wire rst_n,
 20 input wire ddr_ready_done,
 21 //
 22 //sensor_drive
 23 output wire grst,
 24 output reg fst,
 25 output wire dck,
 26 input wire fval,
 27 input wire lval,
 28 input wire do1n,
 29 input wire do2n,
 30 input wire do3n,
 31 input wire do4n,
 32 //output_data
 33 output wire image_data_fs,
 34 output wire image_data_valid,
 35 output wire [13:0]image_data
 36 //
 37 );
 38 //
 39 //*********************************探测器GRST复位*****************************************
 40 //
 41 reg[18:0] cnt_wait00=0;
 42 reg rst;   
 43 //
 44 wire rdempty;
 45 ddr_ready_done_fifo_in    ddr_ready_done_fifo_in_inst ( //1bit@256
 46     .aclr ( 1'b0 ),
 47     .wrclk ( ddr_clk ),
 48     .wrreq ( 1'b1),    
 49     .data ( ddr_ready_done ),
 50     .wrfull(),
 51     .rdclk (clk_160),
 52     .rdreq (!rdempty ),
 53     .q ( rst_n ),
 54     .rdempty (rdempty),
 55     .rdusedw ()
 56 
 57     );
 58 
 59 always@(posedge clk_160)
 60 begin
 61 //        if(cnt_wait00>'d2_200_00)     //6.25 x 2_200_00 = 1.3 ms        
 62         if(cnt_wait00>'d3_276_80)                     
 63           begin 
 64              rst<=1'b1;            
 65              cnt_wait00<='d3_276_81;             
 66           end
 67     else    
 68             begin 
 69              rst<=1'b0;            
 70              cnt_wait00<=cnt_wait00+1'b1;
 71             end
 72 end
 73 
 74 assign grst = ~rst;    
 75 //***********************************ddio***********************************************
 76 //
 77 wire dataout_h1,dataout_l1;    
 78 wire dataout_h2,dataout_l2;    
 79 wire dataout_h3,dataout_l3;    
 80 wire dataout_h4,dataout_l4;
 81 //ddio_in    
 82 ddio_in    ddio_in_inst1 (
 83     .datain ( do1n ),
 84     .inclock ( clk_160 ),
 85     .dataout_h ( dataout_h1 ),
 86     .dataout_l ( dataout_l1 )
 87     );
 88 //
 89 ddio_in    ddio_in_inst2 (
 90     .datain ( do2n ),
 91     .inclock ( clk_160 ),
 92     .dataout_h ( dataout_h2 ),
 93     .dataout_l ( dataout_l2 )
 94     );
 95 //    
 96 ddio_in    ddio_in_inst3 (
 97     .datain ( do3n ),
 98     .inclock ( clk_160 ),
 99     .dataout_h ( dataout_h3 ),
100     .dataout_l ( dataout_l3 )
101     );
102 //
103 ddio_in    ddio_in_inst4 (
104     .datain ( do4n ),
105     .inclock ( clk_160 ),
106     .dataout_h ( dataout_h4 ),
107     .dataout_l ( dataout_l4 )
108     );    
109 //ddio_out    
110 ddio_out    ddio_out_inst (
111     .datain_h ( 1'b1 ),
112     .datain_l ( 1'b0 ),
113     .outclock ( clk_160 ),
114     .dataout ( dck )
115     );    
116 //
117 wire dop1=dataout_l1;
118 wire dop2=dataout_l2;
119 wire dop3=dataout_l3;
120 wire dop4=dataout_l4;
121 //
122 //**************************************状态机*************************************
123 //
124 reg [3:0]  j=0;
125 //
126 reg [7:0] cnt_waitj=0;
127 //
128 reg [12:0] cnt_waitj2=0;
129 //
130 reg [9:0] cnt_lval=0;
131 //
132 reg [29:0] test_dop1 = 0;
133 reg [29:0] test_dop2 = 0;
134 reg [29:0] test_dop3 = 0;
135 reg [29:0] test_dop4 = 0;
136 
137 reg [14:0] buffer_dop1 = 0;
138 reg [14:0] buffer_dop2 = 0;
139 reg [14:0] buffer_dop3 = 0;
140 reg [14:0] buffer_dop4 = 0;
141 
142 reg [3:0] cnt_15 = 0;
143 //
144 reg fval_delay1=0;
145 reg fval_delay2=0;
146 wire fval_pos;
147 wire fval_neg;
148 //
149 reg lval_delay1=0;
150 reg lval_delay2=0;
151 reg lval_delay3=0;
152 //
153 wire lval_pos;
154 //
155 //************************************串并转换******************************************
156 //
157 always@(posedge clk_160)  
158 begin    
159 if(!rst_n  || !(fval&&lval))
160   begin 
161         test_dop1    <=0; 
162         test_dop2    <=0;  
163         test_dop3    <=0; 
164         test_dop4    <=0;
165 //        
166         buffer_dop1  <=0;
167         buffer_dop2  <=0; 
168         buffer_dop3  <=0;  
169         buffer_dop4  <=0;   
170   end
171 else 
172   begin
173         buffer_dop1  <= {dop1,buffer_dop1[14:1]};              
174         buffer_dop2  <= {dop2,buffer_dop2[14:1]};
175         buffer_dop3  <= {dop3,buffer_dop3[14:1]};
176         buffer_dop4  <= {dop4,buffer_dop4[14:1]};
177 //        
178         test_dop1 <= {dop1,test_dop1[29:1]};
179         test_dop2 <= {dop2,test_dop2[29:1]};
180         test_dop3 <= {dop3,test_dop3[29:1]};
181         test_dop4 <= {dop4,test_dop4[29:1]}; 
182     end     
183 end
184 //
185 assign fval_pos = (!fval_delay2)&&fval_delay1;
186 assign fval_neg = (fval_delay2)&& (!fval_delay1);
187 //
188 assign lval_pos = (!lval_delay2)&&lval_delay1;
189 //
190 //*********************************************fst、一行数据接收控制状态机**************************************************
191 always@(posedge clk_160)
192 begin
193 if(!rst_n)
194         begin
195         fst <='d0;            
196         cnt_waitj <=0;
197         cnt_waitj2 <=0;            
198         cnt_lval <='d0;        
199         cnt_15 <='d0;      
200         j <= 6'd0;
201             
202         fval_delay1 <= 0;
203         fval_delay2 <= 0;
204         //
205         lval_delay1 <= 0;
206         lval_delay2 <= 0;
207         lval_delay3 <= 0;    
208 
209         wrreq_sig1<= 1'b0;        
210         end
211 
212 else 
213     begin
214     //
215     fval_delay1 <= fval;
216     fval_delay2 <= fval_delay1;
217     //
218     lval_delay1 <= lval;
219     lval_delay2 <= lval_delay1;
220     lval_delay3 <= lval_delay2;        
221     //
222     case (j)
223     'd0:
224         begin    
225             cnt_waitj2 <= 0;
226             cnt_lval   <= 0;    
227 
228             if(cnt_waitj == 'd255) //fst >= 1us             
229                 begin
230                     fst<= 'd0;
231                     j <= 'd1;
232                     cnt_waitj <= 'd0;
233                 end 
234             else
235                 begin
236                     fst<= 'd1;
237                     j <= 'd0;
238                     cnt_waitj <= cnt_waitj + 1'b1;
239                 end                    
240         end 
241     'd1:
242         begin    
243             if(fval_pos)
244                 begin
245                     j <= 'd2;
246                 end 
247             else
248                 begin
249                     j <= 'd1;            
250                 end     
251         end    
252     'd2:    
253         begin        
254         cnt_waitj2 <= 0;
255         cnt_lval   <= cnt_lval;
256                 
257             if(test_dop1 == {15'b000101000001111,15'b001010101010101} && test_dop2 == {15'b000101100001111,15'b001010101010101} && test_dop3 == {15'b000110000001111,15'b001010101010101} && test_dop4 == {15'b000110100001111,15'b001010101010101} )
258             begin            
259                     j <= 'd3;    //检测头测试字30bit完成则跳转                            
260                     cnt_15 <='d1;
261                 
262                 end 
263             else
264                 begin                                            
265                     j <= 'd2;
266                     cnt_15 <=cnt_15;             
267                 end     
268         end 
269 //        
270     'd3:    
271         begin
272 //            
273             if(cnt_waitj2>'d4814)                
274                 begin
275                     if(cnt_lval=='d1023) // 1024行                    
276                         begin
277                             j<='d4;
278                             cnt_waitj2 <= 0;
279                             cnt_lval   <= 0;                            
280                         end
281                     else 
282                         begin                        
283                             j <= 'd2;
284                             cnt_waitj2 <= 0;
285                             cnt_lval <= cnt_lval + 1'd1;                            
286                         end 
287 //                        
288                         cnt_15 <= 'd0;
289                         wrreq_sig1<= 1'b0;                        
290                 end 
291             else
292                 begin
293                     j <= 'd3;
294                     cnt_waitj2 <= cnt_waitj2 + 1'd1;
295                     cnt_lval <= cnt_lval;
296 //                    
297 //                    if(fval&&lval_delay1)
298                     if(lval_delay1)                    
299                         begin
300                             if(cnt_15 == 'd15)
301                                 begin
302                                     cnt_15 <= 'd1;         
303                                     wrreq_sig1<= 1'b0;
304                                 end 
305                             else if(cnt_15 == 'd14)
306                                 begin
307                                     cnt_15 <= cnt_15 + 1'd1;
308                                     wrreq_sig1<= 1'b1;
309                                 end
310                             else 
311                                 begin
312                                     cnt_15 <= cnt_15 + 1'd1;
313                                     wrreq_sig1<= 1'b0;
314                                 end                        
315                         end
316                     else
317                         begin
318                             cnt_15 <= 'd0;
319                             wrreq_sig1<= 1'b0;
320                         end                     
321 //
322                 end      
323         end
324     'd4:
325         begin    
326             cnt_waitj2 <= 0;
327             cnt_lval   <= 0;
328         
329             if(fval_neg)    
330                 begin        
331                     j <= 'd5;
332                 end
333             else
334                 begin
335                     j <= 'd4;
336                 end                 
337         end 
338     'd5:
339         begin                    
340             if(cnt_waitj == 'd127) 
341                 begin
342                     j <= 'd6;
343                     cnt_waitj <= 0;
344                 end 
345             else
346                 begin
347                     j <= 'd5;
348                     cnt_waitj <= cnt_waitj + 1'b1;
349                 end                  
350         end     
351     'd6:
352         begin        
353             if(cnt_waitj == 'd255)         
354                 begin
355                     fst<= 'd0;
356                     j <= 'd1;
357                     cnt_waitj <= 0;
358                 end 
359             else
360                 begin
361                     fst<= 'd1;
362                     j <= 'd6;
363                     cnt_waitj <= cnt_waitj + 1'b1;
364                 end                 
365         end     
366     default:  
367             begin             
368                 fst <='d0;            
369                 cnt_waitj <='d0;
370                 cnt_waitj2 <='d0;            
371                 cnt_lval <='d0;        
372                 cnt_15 <='d0;      
373                 j <= 6'd0;
374                 //    
375                 fval_delay1 <= 0;
376                 fval_delay2 <= 0;
377                 //
378                 lval_delay1 <= 0;
379                 lval_delay2 <= 0;
380                 lval_delay3 <= 0;     
381                 
382                 wrreq_sig1<= 1'b0;                
383             end
384     endcase
385 
386 end 
387 
388 end 
389 
390 wire [14:0] q_sig1 ;
391 wire [14:0] q_sig2 ;
392 wire [14:0] q_sig3 ;
393 wire [14:0] q_sig4 ;
394 
395 reg [14:0] image_data_out;
396 always@(posedge clk_160)
397 begin
398     if(!rst_n || !(cnt_waitj2 > 'd14))
399     image_data_out <= 'd0;//输出的320个15bit图像数据、不包含头尾测试字
400     else
401         begin
402         
403 //            if(cnt_15 == 'd2 )
404 //                image_data_out  <= 'd6000;
405 //            else if(cnt_15 == 'd6 )
406 //                image_data_out  <= 'd7000;
407 //            else if(cnt_15 == 'd10 )
408 //                image_data_out  <= 'd8000;    
409 //            else if(cnt_15 == 'd14 )
410 //                image_data_out  <= 'd9000;    
411 //            else
412 //                image_data_out  <= image_data_out;
413     
414             if(cnt_15 == 'd2 )
415                 image_data_out  <= 'd32767-q_sig1;
416             else if(cnt_15 == 'd6 )
417                 image_data_out  <= 'd32767-q_sig2;
418             else if(cnt_15 == 'd10 )
419                 image_data_out  <= 'd32767-q_sig3;    
420             else if(cnt_15 == 'd14 )
421                 image_data_out  <= 'd32767-q_sig4;    
422             else
423                 image_data_out  <= image_data_out;
424         end 
425 end
426 //            
427 reg rdreq_sig1 = 1'b0;
428 reg rdreq_sig2 = 1'b0;
429 reg rdreq_sig3 = 1'b0;
430 reg rdreq_sig4 = 1'b0;
431 reg wrreq_sig1 = 1'b0;
432 
433 always@(posedge clk_160)
434 begin
435 if(cnt_waitj2 > 'd13)
436     begin
437         if(cnt_15 == 'd15)
438             begin
439                 rdreq_sig1<= 1'b1;
440                 rdreq_sig2<= 1'b0;
441                 rdreq_sig3<= 1'b0;
442                 rdreq_sig4<= 1'b0;
443             end 
444         else     if(cnt_15 == 'd4)    
445                     begin
446                         rdreq_sig1<= 1'b0;
447                         rdreq_sig2<= 1'b1;
448                         rdreq_sig3<= 1'b0;
449                         rdreq_sig4<= 1'b0;
450                     end
451         else     if(cnt_15 == 'd8)    
452                     begin
453                         rdreq_sig1<= 1'b0;
454                         rdreq_sig2<= 1'b0;
455                         rdreq_sig3<= 1'b1;
456                         rdreq_sig4<= 1'b0;
457                     end
458         else     if(cnt_15 == 'd12)    
459                     begin
460                         rdreq_sig1<= 1'b0;
461                         rdreq_sig2<= 1'b0;
462                         rdreq_sig3<= 1'b0;
463                         rdreq_sig4<= 1'b1;
464                     end            
465         else
466             begin
467                 rdreq_sig1 <= 1'b0;
468                 rdreq_sig2 <= 1'b0;
469                 rdreq_sig3 <= 1'b0;
470                 rdreq_sig4 <= 1'b0;
471             end
472     end     
473 else
474     begin
475         rdreq_sig1 <= 1'b0;
476         rdreq_sig2 <= 1'b0;
477         rdreq_sig3 <= 1'b0;
478         rdreq_sig4 <= 1'b0;
479     end                 
480 end
481 //
482 fifo    fifo_inst1 (
483     .sclr ( lval_pos ),
484     .clock ( clk_160  ),
485     .data  ( buffer_dop1),    
486     .rdreq ( rdreq_sig1 ),
487     .wrreq ( wrreq_sig1 ),
488     .empty (  ),
489     .full  (   ),
490     .q     ( q_sig1     ),
491     .usedw (  )
492     );
493 
494 fifo    fifo_inst2 (
495     .sclr ( lval_pos ),
496     .clock ( clk_160 ),
497     .data  ( buffer_dop2),    
498     .rdreq ( rdreq_sig2 ),
499     .wrreq ( wrreq_sig1 ),
500     .empty (  ),
501     .full  (   ),
502     .q     ( q_sig2     ),
503     .usedw (  )
504     );
505 
506 fifo    fifo_inst3 (
507     .sclr ( lval_pos ),
508     .clock ( clk_160 ),    
509     .data  ( buffer_dop3),    
510     .rdreq ( rdreq_sig3 ),
511     .wrreq ( wrreq_sig1 ),
512     .empty (  ),
513     .full  (   ),
514     .q     ( q_sig3     ),
515     .usedw (  )
516     );
517 
518 fifo    fifo_inst4 (
519     .sclr ( lval_pos ),
520     .clock ( clk_160 ),
521     .data  ( buffer_dop4),    
522     .rdreq ( rdreq_sig4),
523     .wrreq ( wrreq_sig1 ),
524     .empty (  ),
525     .full  (   ),
526     .q     ( q_sig4     ),
527     .usedw (  )
528     );
529         
530 /////////////////////////////////////FIFO test//////////////////////////
531 //
532 reg wrreq_sig = 1'b0;
533 always@(posedge clk_160)
534 begin
535     if(cnt_waitj2 > 'd14)
536         begin
537             if(cnt_15 == 'd3)
538                 wrreq_sig<= 1'b1;
539             else if(cnt_15 == 'd7)
540                         wrreq_sig<= 1'b1;
541             else if(cnt_15 == 'd11)
542                         wrreq_sig<= 1'b1;
543             else if(cnt_15 == 'd15)
544                         wrreq_sig<= 1'b1;        
545             else
546                 wrreq_sig<= 1'b0;
547         end 
548     else 
549         begin
550             wrreq_sig<= 1'b0;
551         end    
552 end 
553 //
554 assign image_data_fs    =  fval_pos;
555 assign image_data_valid    =  wrreq_sig ;//1280X1024
556 assign image_data       =  image_data_out[14:1];
557 //
558 endmodule
559 //