官网

https://github.com/riscv-collab/riscv-gnu-toolchain

编译器

基于RISC-V交叉编译器包括32bit和64bit两种类型，其中每种类型又包括裸机版本（newlib）和动态链接库版本（linux glibc）

• newlib

./configure --prefix=/opt/riscv
make

• glibc

#默认仅支持64位target
./configure --prefix=/opt/riscv
make linux

#仅支持32位target
./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d
make linux

• musl

./configure --prefix=/opt/riscv
make musl

• Newlib/glibc/musl multilib

./configure --prefix=/opt/riscv --enable-multilib
# newlib
make
# glibc
make linux
# musl
make musl

• The multilib compiler will have the prefix riscv64-unknown-elf- or riscv64-unknown-linux-gnu- but will be able to target both 32-bit and 64-bit systems. It will support the most common -march/-mabi options, which can be seen by using the --print-multi-lib flag on either cross-compiler.

# 查看支持的编译架构
 riscv64-unknown-elf-gcc --print-multi-lib

• The musl compiler (riscv64-unknown-linux-musl-) will only be able to target 64-bit systems due to limitations in the upstream musl architecture support. The --enable-multilib flag therefore does not actually enable multilib support for musl libc.

-march and -mabi参数

https://xpack.github.io/dev-tools/riscv-none-elf-gcc/

ISA基础功能

RISC-V ISA strings begin with either RV32I, RV32E, RV64I, or RV128I indicating the supported address space size in bits for the base integer ISA.

• RV32I: A load-store ISA with 32, 32-bit general-purpose integer registers.
• RV32E: An embedded flavour of RV32I with only 16 integer registers.
• RV64I: A 64-bit flavour of RV32I where the general-purpose integer registers are 64-bit wide.

ISA扩展功能

In addition to these base ISAs, a handful of extensions have been specified. The extensions that have both been specified and are supported by the toolchain are:

M - Integer Multiplication and Division
A - Atomics
F - Single-Precision Floating-Point
D - Double-Precision Floating-Point
C - 16-bit Compressed Instructions
G - General, a shortcut to IMAFD

For more details, please see The RISC-V ISA Specification, Volume I: Unprivileged Spec

march

RISC-V ISA strings are defined by appending the supported extensions to the base ISA in the order listed above. For example, the RISC-V ISA with 32, 32-bit integer registers and the instructions to for multiplication would be denoted as “RV32IM”. Users can control the set of instructions that GCC uses when generating assembly code by passing the lower-case ISA string to the -march GCC option: for example -march=rv32im

mabi

除了指定GCC的指令，还可以指定ABI类型，也就是函数调用方式、内存布局

In addition to controlling the instructions available to GCC during code generating (which defines the set of implementations the generated code will run on), users can select from various ABIs to target (which defines the calling convention and layout of objects in memory). Objects and libraries may only be linked together if they follow the same ABI.

RISC-V defines two integer ABIs and three floating-point ABIs, which together are treated as a single ABI string. The integer ABIs follow the standard ABI naming scheme:

• ilp32: “int”, “long”, and pointers are all 32-bit long. “long long” is a 64-bit type, “char” is 8-bit, and “short” is 16-bit.
• lp64: “long” and pointers are 64-bit long, while “int” is a 32-bit type. The other types remain the same as ilp32.

while the floating-point ABIs are a RISC-V specific addition:

• ”” (the empty string): No floating-point arguments are passed in registers.
• f: 32-bit and smaller floating-point arguments are passed in registers. This ABI requires the F extension, as without F there are no floating-point registers.
• d: 64-bit and smaller floating-point arguments are passed in registers. This ABI requires the D extension.

examples

ABI strings are concatenated together and passed via the -mabi argument to GCC. For example:

• -march=rv32imafdc -mabi=ilp32d: Hardware floating-point instructions can be generated and floating-point arguments are passed in registers. This is like the -mfloat-abi=hard option to Arm’s GCC. 架构支持浮点，可生成浮点指令。ABI规定可通过寄存器传参浮点。
• -march=rv32imac -mabi=ilp32: No floating-point instructions can be generated and no floating-point arguments are passed in registers. This is like the -mfloat-abi=soft argument to Arm’s GCC. 架构不支持浮点，不可生成浮点指令。ABI规定不可通过寄存器传参浮点。
• -march=rv32imafdc -mabi=ilp32: Hardware floating-point instructions can be generated, but no floating-point arguments will be passed in registers. This is like the -mfloat-abi=softfp argument to Arm’s GCC, and is usually used when interfacing with soft-float binaries on a hard-float system. 架构支持浮点，可生成浮点指令。但是ABI规定不可通过寄存器传参浮点。也就是硬件支持，但是软件主动不使用硬件浮点功能
• -march=rv32imac -mabi=ilp32d: Illegal, as the ABI requires floating-point arguments are passed in registers but the ISA defines no floating-point registers to pass them in. 非法选项