Application Notes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf
1.2 JTAG background
Today's electronic circuits consist of numerous complex integrated circuits. A typical embedded system can contain multiple CPUs, programmable devices, memory, etc. With such complexity, it is often impossible to directly probe and test the entire functionality of a given design.
In 1990, the Institute of Electrical and Electronics Engineers (IEEE) ratified the standard 1149.1, which was the work of the Joint Test Action Group (JTAG). This standard defines a common means of implementing boundary-scan test functionality in an integrated circuit. It allows devices from different vendors to be present in a common chain to provide access to all of the Input and Output (I/O) pins. Commonly used with additional facilities, such as a bed-of-nails device, it is possible to perform functional and manufacturing tests on an entire circuit. It is common to refer to the IEEE 1149.1 standard as the "JTAG standard". Many published documents and articles use these terms interchangeably.
The IEEE 1149.1 was most recently updated in 2001. Additional IEEE standards reference 1149.1 while providing expanded features such as analog circuit tests in addition to digital circuit tests. These additional standards are 1149.4 - Analog Boundary Scan, 1149.6 - Advanced I/O and 1532 - In System Configuration. The latter is commonly used for programming memory devices and configuring programmable digital logic such as FPGAs and CPLDs.
JTAG (IEEE 1149.1) defines a synchronous state machine consisting of 16 states as noted in Figure 1.1.
