代码如下:
module led_flash(
//端口列表
Clk50M, //时钟信号
Rst_n, //复位信号
led,
);
//端口定义
input Clk50M;
input Rst_n;
output [3:0]led; //led默认为wire类型
reg [24:0]cnt;
parameter CNT_MAX = 25'd24_999_999;
always@(posedge Clk50M or negedge Rst_n) //若遇见Clk上升沿或者Rst下降沿,则:
if(!Rst_n)
cnt <= 25'd0; //非阻塞赋值方式
else if(cnt == CNT_MAX)
cnt <= 25'd0;
else
cnt <= cnt + 1'b1;
reg [3:0]led_r;
// led流水灯1(左移)
// always@(posedge Clk50M or negedge Rst_n)
// if(!Rst_n)
// led_r <= 4'b0001;
// else if(cnt == CNT_MAX)
// begin
// if(led_r == 4'b1000)
// led_r <= 4'b0001;
// else
// led_r <= led_r << 1; //左移操作
// end
// else
// led_r <= led_r;
// led流水灯2(位拼接)
always@(posedge Clk50M or negedge Rst_n)
if(!Rst_n)
led_r <= 4'b0001;
else if(cnt == CNT_MAX)
led_r <= {led_r[2:0],led_r[3]}; //位拼接操作
else
led_r <= led_r;
assign led = ~led_r;
endmodule
标签:cnt,led,FPGA,笔记,001,Rst,input,Clk50M From: https://www.cnblogs.com/little55/p/17827413.html