参考

DDI0487J_a_a-profile_architecture_reference_manual.pdf

• B2.3 Definition of the Arm memory model
  • B2.3.12 Memory barriers
    • Data Memory Barrier (DMB)
    • Data Synchronization Barrier (DSB)
    • Instruction Synchronization Barrier (ISB)

Data Memory Barrier (DMB)

The DMB instruction is a memory barrier instruction that ensures the relative order of memory accesses before the barrier with memory accesses after the barrier. The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order.

The basic principle of a DMB instruction is to introduce order between memory accesses that are specified to be affected by the DMB options supplied as arguments to the DMB instruction. The DMB instruction ensures that all affected memory accesses by the PE executing the DMB instruction that appear in program order before the DMB instruction and those which originate from a different PE, to the extent required by the DMB options, which have been Observed-by the PE before the DMB instruction is executed, are Observed-by each PE, to the extent required by the DMB options, before any affected memory accesses that appear in program order after the DMB instruction are Observed-by that PE.

The DMB instruction affects only memory accesses and the operation of data cache and unified cache maintenance instructions. It has no effect on the ordering of any other instructions executing on the PE.

Data Synchronization Barrier (DSB)

A DSB instruction is a memory barrier that ensures that memory accesses that occur before the DSB instruction have completed before the completion of the DSB instruction. In doing this, it acts as a stronger barrier than a DMB and all ordering that is created by a DMB with specific options is also generated by a DSB with the same options.

A DSB instruction executed by a PE, PEe, completes when all of the following apply:

• All explicit memory effects of the required access types appearing in program order before the DSB are complete for the set of observers in the required shareability domain.

• If the required access types of the DSB is reads and writes, the following instructions issued by PEe before the DSB are complete for the required shareability domain:

  • All cache maintenance instructions.
  • All TLB maintenance instructions.
  • All PSB CYNC instructions.

In addition, no instruction that appears in program order after the DSB instruction can alter any state of the system or perform any part of its functionality until the DSB completes other than:

• Being fetched from memory and decoded.

• Reading the general-purpose, SIMD and floating-point, SVE vector or predicate, Special-purpose, or System registers that are directly or indirectly read without causing side-effects

Instruction Synchronization Barrier (ISB)

An ISB instruction ensures that all instructions that come after the ISB instruction in program order are fetched from the cache or memory after the ISB instruction has completed. Using an ISB ensures that the effects of context-changing operations executed before the ISB are visible to the instructions fetched after the ISB instruction.

Examples of context-changing operations that require the insertion of an ISB instruction to ensure the effects of the operation are visible to instructions fetched after the ISB instruction are:

• Completed cache and TLB maintenance instructions.
• Changes to System registers.

Any context-changing operations appearing in program order after the ISB instruction take effect only after the ISB has been executed.