FPGA 3-8译码器

module decoder_3_8_test(
    a,
    b,
    c,
    out
);
    input a;
    input b;
    input c;
    output reg [7:0]out;
    
    always@(*)begin 
        case({a,b,c})
            3'b000 :out  = 8'b0000_0001;
            3'b001 :out  = 8'b0000_0010;
            3'b010 :out  = 8'b0000_0100;           
            3'b011 :out  = 8'b0000_1000;
            3'b100 :out  = 8'b0001_0000;
            3'b101 :out  = 8'b0010_000;
            3'b110 :out  = 8'b0100_0000;           
            3'b111 :out  = 8'b1000_0000;            
        endcase
    end
endmodule

仿真代码：

`timescale 1ns/1ns
 
module decoder_3_8_test_tb();
    reg s_a;
    reg s_b;
    reg s_c;
    wire [7:0]out;
    
    decoder_3_8_test decoder_3_8_test_tb(
        .a(s_a),
        .b(s_b),
        .c(s_c),
        .out(out)
    );
    initial begin
        s_a=0;s_b=0;s_c=0;
        #200;
        s_a=0;s_b=0;s_c=1;
        #200;
        s_a=0;s_b=1;s_c=0;
        #200;
        s_a=0;s_b=1;s_c=1;
        #200; 
        s_a=1;s_b=0;s_c=0;
        #200;
        s_a=1;s_b=0;s_c=1;
        #200;
        s_a=1;s_b=1;s_c=0;
        #200;
        s_a=1;s_b=1;s_c=1;
        #200;             
        $stop;               
    end
 
endmodule