平台:(正点原子)ZYNQ7020+OV5640
资料:正点原子
参考:
(新建Vitis SDK)https://blog.csdn.net/I_LOVE_MCU/article/details/109456549
(下载程序)https://www.bilibili.com/video/BV11j411f7Co?p=87
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一、ZYNQ配置
(1)波特率
(2)UART串口
(3)DDR
(4)EMIO
(5)S_AXI_HP0
(6)VDMA时钟FCLK_CLK0 =100Mhz
(7)引出端口,改名
二、自定义IP核配置
(1)axi_dynclk_v1_0
(2)DVI_TX
(3)ov5640_cap_data
(4)连接dynck与dvi_transmitter
三、官方IP核配置
(1)v_vid_in_axi4s_0
(2)axi_vdma_0
(3)v_axi4s_vid_out_0
(4)v_tc_0
四、Block Design连线
(1)
(2)
(3)
(4)
(5)
(6)汇总
(7)run automation两次
五、FPGA编程
(1)验证block design
(2)封装顶层文件
(3)输出out product
(4)编写端口约束文件
注意:Block Design中引出的端口一定要和约束文件中一致。
(5)生成比特流
六、SDK编程
(1)导出xsa文件
(2)打开Vitis
(3)创建application工程
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(4)添加文件
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(5)build project
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七、下载程序
SDK
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标签:文件,HDMI,端口,ZYNQ,OV5640,out,SDK From: https://www.cnblogs.com/steven913/p/17366475.html