SystemVerilog for Design Edition 2 Catalog
Catalog：
Chapter 1: Introduction to SystemVerilog
Chapter 2: SystemVerilog Declaration Spaces
Chapter 3: SystemVerilog Literal Values and Built-in Data Types
Chapter 4: SystemVerilog User-Defined and Enumerated Types
Chapter 5: SystemVerilog Arrays, Structures and Unions
Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions
Chapter 7: SystemVerilog Procedural Statements
Chapter 8: Modeling Finite State Machines with SystemVerilog
Chapter 9: SystemVerilog Design Hierarchy
Chapter 10: SystemVerilog Interfaces
Chapter 11: A Complete Design Modeled with SystemVerilog
Chapter 12: Behavioral and Transaction Level Modeling
Topics covered
This book focusses on the portion of SystemVerilog that is intended for representing hardware designs in a manner that is both simulatable and synthesizable.
Chapter 1 presents a brief overview of SystemVerilog and the key enhancements that it adds to the Verilog language.
Chapter 2 discusses the enhancements SystemVerilog provides on where design data can be declared. Packages, $unit, shared variables and other important topics regarding declarations are covered.
Chapter 3 goes into detail on the many new data types SystemVerilog adds to Verilog. The chapter covers the intended and proper usage of these new data types.
Chapter 4 presents user-defined data types, a powerful enhancement to Verilog. The topics include how to create new data type definitions using typedef and defining enumerated type variables.
Chapter 5 looks at using structures and unions in hardware models. The chapter also presents a number of enhancements to arrays, together with suggestions as to how they can be used as abstract, yet synthesizable, hardware modeling constructs.
Chapter 6 presents the specialized procedural blocks, coding blocks and enhanced task and function definitions in SystemVerilog, and how these enhancements will help create models that are correct by design.
Chapter 7 shows how to use the enhancements to Verilog operators and procedural statements to code accurate and deterministic hardware models, using fewer lines of code compared to standard Verilog.
Chapter 8 provides guidelines on how to use enumerated types and specialized procedural blocks for modeling Finite State Machine (FSM) designs. This chapter also presents a number of guidelines on modeling hardware using 2-state logic.
Chapter 9 examines the enhancements to design hierarchy that SystemVerilog provides. Significant constructs are presented, including nested module declarations and simplified module instance declarations.
Chapter 10 discusses the powerful interface construct that SystemVerilog adds to Verilog. Interfaces greatly simplify the representation of complex busses and enable the creation of more intelligent, easier to use IP (intellectual property) models.
Chapter 11 ties together the concepts from all the previous chapters by applying them to a much more extensive example. The example shows a complete model of an ATM switch design, modeled in SystemVerilog.
Chapter 12 provides another complete example of using SystemVerilog. This chapter covers the usage of SystemVerilog to represent models at a much higher level of abstraction, using transactions.
Example: SystemVerilog code sample
module uart (output logic [7:0] data,
output logic data_rdy,
input serial_in);
enum {WAITE, LOAD, READY} State, NextState;
logic [2:0] bit_cnt;
logic cntr_rst, shift_en;
always_ff @(posedge clock, negedge resetN) begin: shifter
if (!resetN)
data <= 8'h0; //reset (active low)
else if (shift_en)
data <= {serial_in, data[7:1]}; //shift right
end: shifter
endmodule
Example testing
Most examples in this book have been tested using the Synopsys VCS® simulator, version 2005.06-SP1, and the Mentor Graphics Questa™ simulator, version 6.2. Most models in this book are synthesizable, and have been tested using the Synopsys DC Compiler™ synthesis compiler, version 2005.12.1