SystemVerilog for Design Edition 2 Chapter 1
Introduction to SystemVerilog:
This chapter provides an overview of SystemVerilog. The topics presented in this chapter include:
• The origins of SystemVerilog
• Technical donations that went into SystemVerilog
• Highlights of key SystemVerilog features
SystemVerilog is a standard set of extensions to the IEEE 1364-2005 Verilog Standard (commonly referred to as “Verilog-2005”).
The SystemVerilog extensions to the Verilog HDL that are described in this book are targeted at design and writing synthesizable
models. These extensions integrate many of the features of the SUPERLOG and C languages. SystemVerilog also contains many extensions for the verification of large designs, integrating features from the SUPERLOG, VERA C, C++, and VHDL languages, along
with OVA and PSL assertions. These verification assertions are in a companion book, SystemVerilog for Verification1.
The following list highlights some of the more significant enhancements SystemVerilog adds to the Verilog HDL for the design and verification of hardware: This list is not intended to be all inclusive of every enhancement to Verilog that is in SystemVerilog. This list just highlights a few key features that aid in writing synthesizable hardware models.
• Interfaces to encapsulate communication and protocol checking within a design
• C like data types, such as int
• User-defined types, using typedef
• Enumerated types
• Type casting
• Structures and unions
• Packages for definitions shared by multiple design blocks
• External compilation-unit scope declarations
• ++, --, += and other assignment operators
• Explicit procedural blocks
• Priority and unique decision modifiers
• Programming statement enhancements
• Pass by reference to tasks, functions and modules